Lines Matching refs:AMDGPU
32 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
33 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
34 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
109 case AMDGPU::CLAMP_R600: {
111 AMDGPU::MOV,
118 case AMDGPU::FABS_R600: {
120 AMDGPU::MOV,
127 case AMDGPU::FNEG_R600: {
129 AMDGPU::MOV,
136 case AMDGPU::MASK_WRITE: {
144 case AMDGPU::MOV_IMM_F32:
149 case AMDGPU::MOV_IMM_I32:
153 case AMDGPU::CONST_COPY: {
154 MachineInstr *NewMI = TII->buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
155 MI->getOperand(0).getReg(), AMDGPU::ALU_CONST);
161 case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
162 case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
163 unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0;
172 case AMDGPU::TXD: {
173 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
174 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
176 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
181 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
186 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_G))
197 case AMDGPU::TXD_SHADOW: {
198 unsigned T0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
199 unsigned T1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
201 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_H), T0)
206 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SET_GRADIENTS_V), T1)
211 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::TEX_SAMPLE_C_G))
222 case AMDGPU::BRANCH:
223 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
227 case AMDGPU::BRANCH_COND_f32: {
229 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
230 AMDGPU::PREDICATE_BIT)
235 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
237 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
241 case AMDGPU::BRANCH_COND_i32: {
243 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X),
244 AMDGPU::PREDICATE_BIT)
249 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP_COND))
251 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
255 case AMDGPU::EG_ExportSwz:
256 case AMDGPU::R600_ExportSwz: {
263 if (NextExportInst->getOpcode() == AMDGPU::EG_ExportSwz ||
264 NextExportInst->getOpcode() == AMDGPU::R600_ExportSwz) {
273 bool EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN)? 1 : 0;
276 unsigned CfInst = (MI->getOpcode() == AMDGPU::EG_ExportSwz)? 84 : 40;
289 case AMDGPU::RETURN: {
330 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
364 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
365 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
373 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
381 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_XY, DL,
383 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
384 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
385 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
386 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
388 interp = DAG.getMachineNode(AMDGPU::INTERP_PAIR_ZW, DL,
390 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
391 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb + 1), MVT::f32),
392 CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
393 AMDGPU::R600_TReg32RegClass.getRegister(2 * ijb), MVT::f32));
418 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
419 AMDGPU::T1_X, VT);
421 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
422 AMDGPU::T1_Y, VT);
424 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
425 AMDGPU::T1_Z, VT);
427 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
428 AMDGPU::T0_X, VT);
430 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
431 AMDGPU::T0_Y, VT);
433 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
434 AMDGPU::T0_Z, VT);
