Lines Matching refs:AMDGPU
52 if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
53 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
56 buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
65 assert(!AMDGPU::R600_Reg128RegClass.contains(DestReg)
66 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
68 MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, AMDGPU::MOV,
77 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::MOV), DebugLoc());
80 MIB.addReg(AMDGPU::ALU_LITERAL_X);
88 return AMDGPU::SETE_INT;
96 case AMDGPU::MOV:
97 case AMDGPU::MOV_IMM_F32:
98 case AMDGPU::MOV_IMM_I32:
109 case AMDGPU::RETURN:
117 case AMDGPU::DOT4_r600_pseudo:
118 case AMDGPU::DOT4_eg_pseudo:
126 case AMDGPU::CUBE_r600_pseudo:
127 case AMDGPU::CUBE_r600_real:
128 case AMDGPU::CUBE_eg_pseudo:
129 case AMDGPU::CUBE_eg_real:
186 if (MI->getOperand(SrcIdx).getReg() == AMDGPU::ALU_CONST) {
205 case AMDGPU::PRED_X:
227 return Opcode == AMDGPU::JUMP || Opcode == AMDGPU::JUMP_COND;
259 if (LastOpc == AMDGPU::JUMP) {
262 } else if (LastOpc == AMDGPU::JUMP_COND) {
270 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
281 if (SecondLastOpc == AMDGPU::JUMP_COND && LastOpc == AMDGPU::JUMP) {
290 Cond.push_back(MachineOperand::CreateReg(AMDGPU::PRED_SEL_ONE, false));
303 case AMDGPU::GPRI32RegClassID: return AMDGPU::BRANCH_COND_i32;
304 case AMDGPU::GPRF32RegClassID: return AMDGPU::BRANCH_COND_f32;
318 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB);
326 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
328 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
336 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND))
338 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
339 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB);
359 case AMDGPU::JUMP_COND: {
365 case AMDGPU::JUMP:
379 case AMDGPU::JUMP_COND: {
385 case AMDGPU::JUMP:
401 case AMDGPU::PRED_SEL_ONE:
402 case AMDGPU::PRED_SEL_ZERO:
403 case AMDGPU::PREDICATE_BIT:
415 if (MI->getOpcode() == AMDGPU::KILLGT) {
481 case AMDGPU::PRED_SEL_ZERO:
482 MO2.setReg(AMDGPU::PRED_SEL_ONE);
484 case AMDGPU::PRED_SEL_ONE:
485 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
516 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
584 unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
587 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
603 return &AMDGPU::R600_TReg32RegClass;
607 return &AMDGPU::TRegMemRegClass;
614 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
615 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
616 AMDGPU::AR_X, OffsetReg);
619 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
621 .addReg(AMDGPU::AR_X, RegState::Implicit);
630 unsigned AddrReg = AMDGPU::R600_AddrRegClass.getRegister(Address);
631 MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, AMDGPU::MOVA_INT_eg,
632 AMDGPU::AR_X,
635 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV,
638 .addReg(AMDGPU::AR_X, RegState::Implicit);
645 return &AMDGPU::IndirectRegRegClass;
683 .addReg(AMDGPU::PRED_SEL_OFF) // $pred_sel
693 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg,
694 AMDGPU::ALU_LITERAL_X);
