Lines Matching full:src0
108 bits<11> src0;
118 bits<9> src0_sel = src0{8-0};
119 bits<2> src0_chan = src0{10-9};
278 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
282 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
306 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))]
318 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
323 "$src0_neg$src0_abs$src0$src0_sel$src0_abs$src0_rel, "
342 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
355 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
360 "$src0_neg$src0$src0_sel$src0_rel, "
390 (ins R600_Reg128:$src0, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
391 !strconcat(opName, "$dst, $src0, $resourceId, $samplerId, $textureTarget"),
504 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
505 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
510 (ins i32imm:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
511 "INTERP_PAIR_ZW $src0 $src1 $src2 : $dst0 dst1",
525 (ins i32imm:$src0),
526 "INTERP_LOAD $src0 : $dst",
693 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
700 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
707 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
714 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
721 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
728 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
735 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
742 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, (i32 -1), (i32 0),
802 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
808 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
814 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
820 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
826 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
832 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
843 (selectcc (i32 R600_Reg32:$src0), 0,
851 (selectcc (i32 R600_Reg32:$src0), 0,
859 (selectcc (i32 R600_Reg32:$src0), 0,
870 [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
872 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $resourceId, $samplerId, $textureTarget";
873 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget);
878 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
883 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
888 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
903 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
908 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
913 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
918 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
923 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0,imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
928 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
958 (fadd (fmul R600_Reg32:$src0, R600_Reg32:$src1), R600_Reg32:$src2))]
964 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
972 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
980 (selectcc (f32 R600_Reg32:$src0), FP_ZERO,
988 (ins R600_Reg128:$src0, R600_Reg128:$src1),
989 "DOT4 $dst $src0, $src1",
990 [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))]
1061 inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))]
1092 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
1093 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1097 (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
1098 (MUL_IEEE R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
1228 // Src0 = Input
1242 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
1249 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1295 def : Pat<(fp_to_sint R600_Reg32:$src0),
1296 (FLT_TO_INT_eg (TRUNC R600_Reg32:$src0))>;
1298 def : Pat<(fp_to_uint R600_Reg32:$src0),
1299 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src0))>;
1557 (AMDGPUurecip R600_Reg32:$src0),
1558 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1587 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
1629 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1630 "TXD $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1631 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, imm:$textureTarget))]
1636 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$resourceId, i32imm:$samplerId, i32imm:$textureTarget),
1637 "TXD_SHADOW $dst, $src0, $src1, $src2, $resourceId, $samplerId, $textureTarget",
1638 [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, imm:$resourceId, imm:$samplerId, TEX_SHADOW:$textureTarget))]
1855 (selectcc (i32 R600_Reg32:$src0), 0, (f32 R600_Reg32:$src1),
1857 (cnd R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
1866 (selectcc (i32 R600_Reg32:$src0), -1, (i32 R600_Reg32:$src1),
1868 (CNDGE_INT R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2)
1878 (int_AMDGPU_kill R600_Reg32:$src0),
1879 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
1884 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1885 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1890 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1891 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1896 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LT),
1897 (SETGT_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
1902 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, COND_LE),
1903 (SETGE_DX10 R600_Reg32:$src1, R600_Reg32:$src0)
1908 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1909 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1914 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1915 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1920 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1921 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1926 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1927 (SETGE_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1940 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1941 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1946 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETO),
1947 (SETE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
1952 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1953 (SNE R600_Reg32:$src0, R600_Reg32:$src1)
1958 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUO),
1959 (SETNE_DX10 R600_Reg32:$src0, R600_Reg32:$src1)
