Lines Matching refs:AMDGPU
17 #include "AMDGPU.h"
35 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
36 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
38 addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
39 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
40 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
42 addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
43 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
45 addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
47 addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
48 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
50 addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
51 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
53 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
54 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
56 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
57 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
146 CCInfo.AllocateReg(AMDGPU::VGPR0);
147 CCInfo.AllocateReg(AMDGPU::VGPR1);
167 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
168 &AMDGPU::SReg_64RegClass);
169 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
217 case AMDGPU::BRANCH: return BB;
218 case AMDGPU::SI_WQM:
227 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC)
228 .addReg(AMDGPU::EXEC);
419 return AMDGPU::VSrc_32RegClassID == RegClass ||
420 AMDGPU::VSrc_64RegClassID == RegClass;
425 return AMDGPU::SSrc_32RegClassID == RegClass ||
426 AMDGPU::SSrc_64RegClassID == RegClass;
524 if (RegClass == AMDGPU::VSrc_32RegClassID)
525 RegClass = AMDGPU::VReg_32RegClassID;
526 else if (RegClass == AMDGPU::VSrc_64RegClassID)
527 RegClass = AMDGPU::VReg_64RegClassID;
560 int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
