Lines Matching refs:AMDGPU
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
46 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
47 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
48 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
49 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15, 0
53 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
54 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7, 0
58 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, 0
62 AMDGPU::sub0, AMDGPU::sub1, 0
68 if (AMDGPU::SReg_32RegClass.contains(DestReg)) {
69 assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
70 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
74 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
75 assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
76 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
80 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) {
81 assert(AMDGPU::SReg_128RegClass.contains(SrcReg));
82 Opcode = AMDGPU::S_MOV_B32;
85 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) {
86 assert(AMDGPU::SReg_256RegClass.contains(SrcReg));
87 Opcode = AMDGPU::S_MOV_B32;
90 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) {
91 assert(AMDGPU::SReg_512RegClass.contains(SrcReg));
92 Opcode = AMDGPU::S_MOV_B32;
95 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
96 assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
97 AMDGPU::SReg_32RegClass.contains(SrcReg));
98 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
102 } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) {
103 assert(AMDGPU::VReg_64RegClass.contains(SrcReg) ||
104 AMDGPU::SReg_64RegClass.contains(SrcReg));
105 Opcode = AMDGPU::V_MOV_B32_e32;
108 } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) {
109 assert(AMDGPU::VReg_128RegClass.contains(SrcReg) ||
110 AMDGPU::SReg_128RegClass.contains(SrcReg));
111 Opcode = AMDGPU::V_MOV_B32_e32;
114 } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) {
115 assert(AMDGPU::VReg_256RegClass.contains(SrcReg) ||
116 AMDGPU::SReg_256RegClass.contains(SrcReg));
117 Opcode = AMDGPU::V_MOV_B32_e32;
120 } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) {
121 assert(AMDGPU::VReg_512RegClass.contains(SrcReg) ||
122 AMDGPU::SReg_512RegClass.contains(SrcReg));
123 Opcode = AMDGPU::V_MOV_B32_e32;
153 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_B32_e32), DebugLoc());
165 case AMDGPU::S_MOV_B32:
166 case AMDGPU::S_MOV_B64:
167 case AMDGPU::V_MOV_B32_e32:
168 case AMDGPU::V_MOV_B32_e64:
175 return RC != &AMDGPU::EXECRegRegClass;
