Lines Matching full:src0
79 op, (outs SReg_32:$dst), (ins SSrc_32:$src0),
80 opName#" $dst, $src0", pattern
84 op, (outs SReg_64:$dst), (ins SSrc_64:$src0),
85 opName#" $dst, $src0", pattern
89 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
90 opName#" $dst, $src0, $src1", pattern
94 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
95 opName#" $dst, $src0, $src1", pattern
99 op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
100 opName#" $dst, $src0, $src1", pattern
104 op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
105 opName#" $dst, $src0, $src1", pattern
109 op, (outs SReg_32:$dst), (ins i16imm:$src0),
110 opName#" $dst, $src0", pattern
114 op, (outs SReg_64:$dst), (ins i16imm:$src0),
115 opName#" $dst, $src0", pattern
145 op, (outs drc:$dst), (ins src:$src0),
146 opName#"_e32 $dst, $src0", pattern
152 (ins src:$src0,
155 opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
171 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
172 opName#"_e32 $dst, $src0, $src1", pattern
178 (ins arc:$src0, arc:$src1,
181 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
196 op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
197 opName#"_e32 $dst, $src0, $src1", pattern
203 (ins VSrc_32:$src0, VSrc_32:$src1,
206 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
220 op, (ins arc:$src0, vrc:$src1),
221 opName#"_e32 $dst, $src0, $src1", []
227 (ins arc:$src0, arc:$src1,
230 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg",
232 [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
249 (ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
251 opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
256 (ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
258 opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
