Lines Matching full:src0
109 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
111 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))]
597 [(set VReg_32:$dst, (sint_to_fp VSrc_32:$src0))]
602 [(set (i32 VReg_32:$dst), (fp_to_sint VSrc_32:$src0))]
619 [(set VReg_32:$dst, (AMDGPUfract VSrc_32:$src0))]
623 [(set VReg_32:$dst, (fceil VSrc_32:$src0))]
626 [(set VReg_32:$dst, (frint VSrc_32:$src0))]
629 [(set VReg_32:$dst, (ffloor VSrc_32:$src0))]
632 [(set VReg_32:$dst, (fexp2 VSrc_32:$src0))]
636 [(set VReg_32:$dst, (flog2 VSrc_32:$src0))]
641 [(set VReg_32:$dst, (fdiv FP_ONE, VSrc_32:$src0))]
647 [(set VReg_32:$dst, (int_AMDGPU_rsq VSrc_32:$src0))]
685 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
686 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]",
689 let Constraints = "$src0 = $dst";
690 let DisableEncoding = "$src0,$m0";
697 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0),
698 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]",
779 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc),
780 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]",
787 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2,
789 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg",
791 VSrc_32:$src1, VSrc_32:$src0))]
796 (f32 (select (i1 SSrc_64:$src2), VSrc_32:$src1, VSrc_32:$src0)),
797 (V_CNDMASK_B32_e64 VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2)
805 [(set VReg_32:$dst, (fadd VSrc_32:$src0, VReg_32:$src1))]
810 [(set VReg_32:$dst, (fsub VSrc_32:$src0, VReg_32:$src1))]
820 [(set VReg_32:$dst, (int_AMDGPU_mul VSrc_32:$src0, VReg_32:$src1))]
824 [(set VReg_32:$dst, (fmul VSrc_32:$src0, VReg_32:$src1))]
837 [(set VReg_32:$dst, (AMDGPUfmin VSrc_32:$src0, VReg_32:$src1))]
841 [(set VReg_32:$dst, (AMDGPUfmax VSrc_32:$src0, VReg_32:$src1))]
858 [(set VReg_32:$dst, (shl VSrc_32:$src0, (i32 VReg_32:$src1)))]
865 [(set VReg_32:$dst, (and VSrc_32:$src0, VReg_32:$src1))]
868 [(set VReg_32:$dst, (or VSrc_32:$src0, VReg_32:$src1))]
871 [(set VReg_32:$dst, (xor VSrc_32:$src0, VReg_32:$src1))]
887 [(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
892 [(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
907 [(set VReg_32:$dst, (int_SI_packf16 VSrc_32:$src0, VReg_32:$src1))]
978 (mul VSrc_32:$src0, VReg_32:$src1),
979 (V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0)
1003 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32",
1005 SReg_32:$src0, SReg_32:$src1))]
1012 (f32 (select (i1 SCCReg:$scc), SReg_32:$src0, SReg_32:$src1)),
1013 (S_CSELECT_B32 SReg_32:$src0, SReg_32:$src1, SCCReg:$scc)
1019 [(set SReg_64:$dst, (i64 (and SSrc_64:$src0, SSrc_64:$src1)))]
1023 (i1 (and SSrc_64:$src0, SSrc_64:$src1)),
1024 (S_AND_B64 SSrc_64:$src0, SSrc_64:$src1)
1030 (i1 (or SSrc_64:$src0, SSrc_64:$src1)),
1031 (S_OR_B64 SSrc_64:$src0, SSrc_64:$src1)
1130 (ins SReg_64:$src0, SReg_64:$src1),
1131 "SI_ELSE_BREAK $dst, $src0, $src1",
1132 [(set SReg_64:$dst, (int_SI_else_break SReg_64:$src0, SReg_64:$src1))]
1180 (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2),
1181 (V_CNDMASK_B32_e64 VReg_32:$src2, VReg_32:$src1, (V_CMP_GT_F32_e64 0, VReg_32:$src0))
1201 VReg_32:$src0,VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
1203 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3)
1449 (int_AMDGPU_div VSrc_32:$src0, VSrc_32:$src1),
1450 (V_MUL_LEGACY_F32_e32 VSrc_32:$src0, (V_RCP_LEGACY_F32_e32 VSrc_32:$src1))
1454 (fdiv VSrc_32:$src0, VSrc_32:$src1),
1455 src0, (V_RCP_F32_e32 VSrc_32:$src1))
1459 (fcos VSrc_32:$src0),
1460 (V_COS_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1464 (fsin VSrc_32:$src0),
1465 (V_SIN_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
1490 (i32 (sext (i1 SReg_64:$src0))),
1491 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), SReg_64:$src0)
1516 def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)),
1517 (V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
