Lines Matching defs:Copy
1615 // Copy the result values into the output registers.
1650 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1680 // The x86-64 ABIs require that for returning structs by value we copy
1683 // so now we copy the value out and into %rax/%eax.
1718 SDNode *Copy = *N->use_begin();
1719 if (Copy->getOpcode() == ISD::CopyToReg) {
1720 // If the copy has a glue operand, we conservatively assume it isn't safe to
1722 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1724 TCChain = Copy->getOperand(0);
1725 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1729 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1774 // Copy all of the result registers out of their specified physreg.
1789 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1793 // If we prefer to use the value in xmm registers, copy it out as f80 and
1864 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1866 /// the specific parameter attribute. The copy will be passed as a byval
2050 // The x86-64 ABIs require that for returning structs by value we copy
2062 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2514 // Copy relative to framepointer.
2545 // Build a sequence of copy-to-reg nodes chained together with token chain
2546 // and flag operands which copy the outgoing args into registers.
2635 // Returns a chain & a flag for retval copy to use.
2694 // Returns a flag for retval copy to use.
7128 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12774 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13107 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
13131 // Copy PhyReg back from virtual register.
13132 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
13145 // Copy PhyReg back to virtual register.
13146 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
13156 TII->get(TargetOpcode::COPY), DstReg)
13423 // Copy EDX:EAX back from HiReg:LoReg
13424 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
13425 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
13426 // Copy ECX:EBX from t1H:t1L
13427 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
13428 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
13439 // Copy EDX:EAX back to t3H:t3L
13440 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
13441 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
13450 TII->get(TargetOpcode::COPY), DstLoReg)
13453 TII->get(TargetOpcode::COPY), DstHiReg)
13491 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13528 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13548 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13550 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13764 // If we need to align it, do so. Otherwise, just copy the address
13780 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13953 // live into the sink and copy blocks.
14050 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14060 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
14062 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
14091 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
17008 std::copy(Mask.begin(), Mask.end(), LMask.begin());
17026 std::copy(Mask.begin(), Mask.end(), RMask.begin());
