Lines Matching defs:SHL
498 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
795 setOperationAction(ISD::SHL, VT, Expand);
1050 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1051 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1060 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1061 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1068 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1069 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1133 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1134 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1192 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1193 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1218 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1325 setTargetDAGCombine(ISD::SHL);
4913 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
6108 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
7885 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7923 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
9140 if (Op1.getOpcode() == ISD::SHL)
9142 if (Op0.getOpcode() == ISD::SHL) {
10555 Opcode = ISD::SHL;
11504 // Optimize shl/srl/sra with constant shift amount.
11513 if (Op.getOpcode() == ISD::SHL)
11525 if (Op.getOpcode() == ISD::SHL) {
11527 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11529 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11534 return DAG.getNode(ISD::AND, dl, VT, SHL,
11569 if (Op.getOpcode() == ISD::SHL) {
11571 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11573 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11578 return DAG.getNode(ISD::AND, dl, VT, SHL,
11614 // Lower SHL with variable shift amount.
11615 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11616 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
11623 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11627 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
11963 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12162 case ISD::SHL: return LowerShift(Op, DAG);
15360 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15700 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15814 /// LEA + SHL, LEA + LEA.
15856 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15863 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15881 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
15893 Mask = Mask.shl(ShAmt);
15902 // shl.
15903 // (shl V, 1) -> add V,V
15924 if (N->getOpcode() == ISD::SHL) {
16009 case ISD::SHL:
16392 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16394 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17593 case ISD::SHL:
17657 case ISD::SHL:
17703 case ISD::SHL:
17706 // Look out for (store (shl (load), x)).
