Lines Matching refs:getOpcode
76 if (Vec.getOpcode() == ISD::UNDEF)
89 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 if (Vec.getOpcode() == ISD::UNDEF)
1719 if (Copy->getOpcode() == ISD::CopyToReg) {
1725 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1731 if (UI->getOpcode() != X86ISD::RET_FLAG)
2773 if (Arg.getOpcode() == ISD::CopyFromReg) {
2784 unsigned Opcode = Def->getOpcode();
2805 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
4290 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4303 if (N->getOpcode() != ISD::BUILD_VECTOR)
4308 switch (N->getOperand(i).getNode()->getOpcode()) {
4356 if (N->getOpcode() != ISD::BUILD_VECTOR)
4376 unsigned Opc = V2.getOpcode();
4383 unsigned Opc = V1.getOpcode();
4615 switch(N->getOpcode()) {
4696 unsigned Opcode = V.getOpcode();
4741 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4745 if (V.getOpcode() == ISD::BUILD_VECTOR)
4762 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
5075 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5078 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5084 if (Elt.getOpcode() == ISD::UNDEF)
5155 switch (Op.getOpcode()) {
5166 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5167 Ld.getOpcode() == ISD::ConstantFP);
5186 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5187 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5199 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5200 Ld.getOpcode() == ISD::ConstantFP);
5283 unsigned Opc = Op.getOperand(i).getOpcode();
5381 if (Elt.getOpcode() == ISD::UNDEF)
5384 if (Elt.getOpcode() != ISD::Constant &&
5385 Elt.getOpcode() != ISD::ConstantFP)
5624 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5630 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5641 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5659 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5947 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5971 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6051 if (V2.getOpcode() == ISD::UNDEF ||
6149 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6240 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6241 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6518 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6521 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6523 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6524 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6570 if (V2.getOpcode() == ISD::UNDEF)
6655 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6690 if (V1.getOpcode() == ISD::BITCAST &&
6691 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6692 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6788 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6789 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7136 if ((User->getOpcode() != ISD::STORE ||
7139 (User->getOpcode() != ISD::BITCAST ||
7912 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7921 if (Op.getOpcode() == ISD::SHL_PARTS) {
7939 if (Op.getOpcode() == ISD::SHL_PARTS) {
8386 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8779 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8802 if (I->getOpcode() == ISD::OR) {
8811 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8907 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8911 switch (Arith.getOpcode()) {
8927 switch (ArithOp.getOpcode()) {
8941 if (UI->getOpcode() != ISD::CopyToReg &&
8942 UI->getOpcode() != ISD::SETCC &&
8943 UI->getOpcode() != ISD::STORE)
8975 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8981 if (User->getOpcode() != ISD::BRCOND &&
8982 User->getOpcode() != ISD::SETCC &&
8983 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9000 if (UI->getOpcode() == ISD::STORE)
9004 switch (ArithOp.getOpcode()) {
9045 switch (WideVal.getOpcode()) {
9056 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9105 Cmp.getOpcode() != X86ISD::CMP ||
9134 if (Op0.getOpcode() == ISD::TRUNCATE)
9136 if (Op1.getOpcode() == ISD::TRUNCATE)
9140 if (Op1.getOpcode() == ISD::SHL)
9142 if (Op0.getOpcode() == ISD::SHL) {
9158 } else if (Op1.getOpcode() == ISD::Constant) {
9163 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9179 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
9215 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9236 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9237 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9410 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9411 Op1.getOpcode() == ISD::Constant &&
9421 if (Op1.getOpcode() == ISD::Constant &&
9428 if (Op0.getOpcode() == X86ISD::SETCC) {
9453 unsigned Opc = Op.getNode()->getOpcode();
9483 if (V.getOpcode() != ISD::TRUNCATE)
9500 if (Cond.getOpcode() == ISD::SETCC) {
9510 if (Cond.getOpcode() == X86ISD::SETCC &&
9511 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9557 if (Cond.getOpcode() == ISD::AND &&
9558 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9566 unsigned CondOpcode = Cond.getOpcode();
9572 unsigned Opc = Cmp.getOpcode();
9627 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9646 if (Cond.getOpcode() == X86ISD::SUB) {
9664 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9668 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9733 Opc = Op.getOpcode();
9736 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9738 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9745 if (Op.getOpcode() != ISD::XOR)
9749 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9764 if (Cond.getOpcode() == ISD::SETCC) {
9770 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9771 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9772 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9773 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9774 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9775 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9786 else if (Cond.getOpcode() == X86ISD::ADD ||
9787 Cond.getOpcode() == X86ISD::SUB ||
9788 Cond.getOpcode() == X86ISD::SMUL ||
9789 Cond.getOpcode() == X86ISD::UMUL)
9794 if (Cond.getOpcode() == ISD::AND &&
9795 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9803 unsigned CondOpcode = Cond.getOpcode();
9809 unsigned Opc = Cmp.getOpcode();
9827 CondOpcode = Cond.getOpcode();
9897 if (User->getOpcode() == ISD::BR) {
9926 } else if (Cond.getOpcode() == ISD::SETCC &&
9938 if (User->getOpcode() == ISD::BR) {
9957 } else if (Cond.getOpcode() == ISD::SETCC &&
9969 if (User->getOpcode() == ISD::BR) {
9998 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
11360 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11361 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11513 if (Op.getOpcode() == ISD::SHL)
11516 if (Op.getOpcode() == ISD::SRL)
11519 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11525 if (Op.getOpcode() == ISD::SHL) {
11537 if (Op.getOpcode() == ISD::SRL) {
11549 if (Op.getOpcode() == ISD::SRA) {
11569 if (Op.getOpcode() == ISD::SHL) {
11581 if (Op.getOpcode() == ISD::SRL) {
11593 if (Op.getOpcode() == ISD::SRA) {
11615 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11623 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11680 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11700 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11701 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11721 switch (Op.getOpcode()) {
11822 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
11823 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
12044 switch (Op.getOpcode()) {
12099 switch (Op.getOpcode()) {
12233 switch (N->getOpcode()) {
12245 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12362 switch (N->getOpcode()) {
12655 if (Val.getOpcode() != ISD::LOAD)
13020 unsigned Opc = MI->getOpcode();
13324 unsigned Opc = MI->getOpcode();
13466 switch (MI->getOpcode()) {
13503 switch (MI->getOpcode()) {
14426 switch (MI->getOpcode()) {
14500 switch (MI->getOpcode()) {
14660 unsigned Opc = Op.getOpcode();
14724 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14736 if (N->getOpcode() == X86ISD::Wrapper) {
14789 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14790 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14801 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14802 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14803 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14887 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14931 if (InVec.getOpcode() == ISD::BITCAST) {
14942 if (!isTargetShuffle(InVec.getOpcode()))
14965 if (LdNode.getOpcode() == ISD::BITCAST) {
15020 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15043 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15050 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15051 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
15190 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
15342 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15343 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15438 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15456 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15481 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15486 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15499 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15511 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15520 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15559 if (Cmp.getOpcode() != X86ISD::CMP &&
15560 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15590 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
15593 switch (SetCC.getOpcode()) {
15611 if (Op.getOpcode() != X86ISD::RDRAND)
15654 switch (Cond.getOpcode()) {
15789 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
15848 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15884 N1C && N0.getOpcode() == ISD::AND &&
15885 N0.getOperand(1).getOpcode() == ISD::Constant) {
15887 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
15888 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15889 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15890 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
15924 if (N->getOpcode() == ISD::SHL) {
15945 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15950 if (Arg.getOpcode() == ISD::UNDEF) continue;
15961 if (Arg.getOpcode() == ISD::UNDEF) continue;
15966 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15969 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15974 if (Arg.getOpcode() == ISD::UNDEF) continue;
15978 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16006 switch (N->getOpcode()) {
16061 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
16073 switch (UI->getOpcode()) {
16130 if (N->getOpcode() == ISD::BITCAST)
16136 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
16140 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
16141 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
16161 assert((N->getOpcode() == ISD::ANY_EXTEND ||
16162 N->getOpcode() == ISD::ZERO_EXTEND ||
16163 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
16170 if (Narrow->getOpcode() != ISD::XOR &&
16171 Narrow->getOpcode() != ISD::AND &&
16172 Narrow->getOpcode() != ISD::OR)
16180 if (N0.getOpcode() != ISD::TRUNCATE)
16189 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16197 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
16212 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16213 unsigned Opcode = N->getOpcode();
16252 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16257 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16262 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16267 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16286 if (N0.getOpcode() == ISD::XOR &&
16292 if (N1.getOpcode() == ISD::XOR &&
16321 if (N0.getOpcode() == X86ISD::ANDNP)
16324 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16339 if (Mask.getOpcode() == ISD::BITCAST)
16341 if (X.getOpcode() == ISD::BITCAST)
16343 if (Y.getOpcode() == ISD::BITCAST)
16351 if (Mask.getOpcode() != X86ISD::VSRAI)
16366 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16392 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16394 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16405 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16407 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16414 if (ShAmt0.getOpcode() == ISD::SUB) {
16421 if (ShAmt1.getOpcode() == ISD::SUB) {
16425 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16461 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16462 N0.getOpcode() == ISD::ADD &&
16464 N1.getOpcode() == ISD::SRA &&
16509 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16513 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16867 ChainVal->getOpcode() == ISD::TokenFactor) {
16976 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16977 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17002 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17003 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17005 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17010 if (LHS.getOpcode() != ISD::UNDEF)
17020 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17021 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17023 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17028 if (RHS.getOpcode() != ISD::UNDEF)
17108 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
17123 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
17132 switch (N->getOpcode()) {
17176 if (Op.getOpcode() == ISD::BITCAST)
17179 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
17203 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
17204 N0.getOpcode() == ISD::SIGN_EXTEND)) {
17209 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
17259 bool NegA = (A.getOpcode() == ISD::FNEG);
17260 getOpcode() == ISD::FNEG);
17261 bool NegC = (C.getOpcode() == ISD::FNEG);
17292 if (N0.getOpcode() == ISD::AND &&
17296 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
17323 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17331 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17367 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17433 if (Op0.getOpcode() == ISD::LOAD) {
17482 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17483 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17487 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
17495 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
17504 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17506 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17509 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17541 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17569 while (In.getOpcode() == ISD::BITCAST)
17572 if (In.getOpcode() != X86ISD::VZEXT)
17582 switch (N->getOpcode()) {
17679 switch (Op.getOpcode()) {
17691 if (UI->getOpcode() != ISD::CopyToReg)
18110 } else if (Op.getOpcode() == ISD::ADD) {
18116 } else if (Op.getOpcode() == ISD::SUB) {
