Lines Matching refs:getOpcode
1377 switch (MI.getOpcode()) {
1400 switch (MI.getOpcode()) {
1501 if (isFrameLoadOpcode(MI->getOpcode()))
1509 if (isFrameLoadOpcode(MI->getOpcode())) {
1522 if (isFrameStoreOpcode(MI->getOpcode()))
1531 if (isFrameStoreOpcode(MI->getOpcode())) {
1552 if (DefMI->getOpcode() != X86::MOVPC32r)
1563 switch (MI->getOpcode()) {
1730 unsigned Opc = Orig->getOpcode();
1906 unsigned MIOpc = MI->getOpcode();
2161 switch (MI->getOpcode()) {
2170 switch (MI->getOpcode()) {
2206 switch (MI->getOpcode()) {
2547 if (I->getOpcode() == X86::JMP_4) {
2577 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2674 if (I->getOpcode() != X86::JMP_4 &&
2675 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
3057 switch (MI->getOpcode()) {
3135 if (((FlagI->getOpcode() == X86::CMP64rr &&
3136 OI->getOpcode() == X86::SUB64rr) ||
3137 (FlagI->getOpcode() == X86::CMP32rr &&
3138 OI->getOpcode() == X86::SUB32rr)||
3139 (FlagI->getOpcode() == X86::CMP16rr &&
3140 OI->getOpcode() == X86::SUB16rr)||
3141 (FlagI->getOpcode() == X86::CMP8rr &&
3142 OI->getOpcode() == X86::SUB8rr)) &&
3149 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3150 OI->getOpcode() == X86::SUB64ri32) ||
3151 (FlagI->getOpcode() == X86::CMP64ri8 &&
3152 OI->getOpcode() == X86::SUB64ri8) ||
3153 (FlagI->getOpcode() == X86::CMP32ri &&
3154 OI->getOpcode() == X86::SUB32ri) ||
3155 (FlagI->getOpcode() == X86::CMP32ri8 &&
3156 OI->getOpcode() == X86::SUB32ri8) ||
3157 (FlagI->getOpcode() == X86::CMP16ri &&
3158 OI->getOpcode() == X86::SUB16ri) ||
3159 (FlagI->getOpcode() == X86::CMP16ri8 &&
3160 OI->getOpcode() == X86::SUB16ri8) ||
3161 (FlagI->getOpcode() == X86::CMP8ri &&
3162 OI->getOpcode() == X86::SUB8ri)) &&
3172 switch (MI->getOpcode()) {
3218 switch (CmpInstr->getOpcode()) {
3238 switch (CmpInstr->getOpcode()) {
3311 if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 ||
3312 Instr->getOpcode() == X86::MOV16r0 ||
3313 Instr->getOpcode() == X86::MOV32r0 ||
3314 Instr->getOpcode() == X86::MOV64r0) &&
3358 OldCC = getCondFromBranchOpc(Instr.getOpcode());
3360 OldCC = getCondFromSETOpc(Instr.getOpcode());
3364 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3545 switch (MI->getOpcode()) {
3665 if (MI->getOpcode() == X86::ADD32ri &&
3681 switch (MI->getOpcode()) {
3706 OpcodeTablePtr->find(MI->getOpcode());
3815 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3869 hasPartialRegUpdate(MI->getOpcode()))
3878 switch (MI->getOpcode()) {
3911 hasPartialRegUpdate(MI->getOpcode()))
3919 switch (LoadMI->getOpcode()) {
3939 switch (MI->getOpcode()) {
3958 switch (LoadMI->getOpcode()) {
3989 unsigned Opc = LoadMI->getOpcode();
4013 if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4014 LoadMI->getOpcode() == X86::VMOVSSrm) &&
4020 if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4021 LoadMI->getOpcode() == X86::VMOVSDrm) &&
4045 switch (MI->getOpcode()) {
4065 unsigned Opc = MI->getOpcode();
4102 MemOp2RegOpTable.find(MI->getOpcode());
4180 switch (DataMI->getOpcode()) {
4193 switch (DataMI->getOpcode()) {
4628 if (domain && lookup(MI->getOpcode(), domain))
4630 else if (domain && lookupAVX2(MI->getOpcode(), domain))
4639 const uint16_t *table = lookup(MI->getOpcode(), dom);
4643 table = lookupAVX2(MI->getOpcode(), dom);
4705 return isHighLatencyDef(DefMI->getOpcode());
4805 switch (I->getOpcode()) {
