Lines Matching refs:VX
820 /* The VA field in a VA, VX or VXR form instruction. */
824 /* The VB field in a VA, VX or VXR form instruction. */
832 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
837 /* The SIMM field in a VX form instruction. */
841 /* The UIMM field in a VX form instruction, and TE in Z form. */
1717 /* An VX form instruction. */
1718 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1720 /* The mask for an VX form instruction. */
1721 #define VX_MASK VX(0x3f, 0x7ff)
2147 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
2148 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
2153 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
2154 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
2155 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
2156 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
2157 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
2158 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
2159 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
2160 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
2161 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2162 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2163 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2164 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2165 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2166 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2167 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
2168 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
2169 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
2170 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
2171 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
2172 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
2173 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
2174 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
2175 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
2176 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
2177 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
2178 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
2179 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
2180 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
2181 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
2184 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
2185 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
2186 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
2187 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
2188 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
2189 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
2190 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
2191 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
2192 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
2193 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
2194 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
2195 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
2196 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
2197 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
2198 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
2199 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
2200 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
2201 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
2202 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
2203 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2204 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2231 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2232 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2233 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2234 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2236 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2237 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2238 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2239 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2240 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2241 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2242 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2245 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2246 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2247 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2248 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2249 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2250 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2251 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2253 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2254 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2255 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2256 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2257 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2258 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2265 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2266 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2267 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2268 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2269 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2270 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2271 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2272 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2274 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2275 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2277 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2278 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2279 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2280 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2281 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2282 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2283 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2284 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2285 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2286 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2287 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2288 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2289 VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2290 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2291 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2292 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2293 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2294 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2296 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2297 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2299 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2300 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2301 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2302 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2303 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2304 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2305 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2306 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2307 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2308 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2309 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2310 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2311 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2312 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2313 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2314 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2315 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2316 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2317 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2318 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2319 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2320 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2321 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2322 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2323 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2324 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2325 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2326 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2327 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2328 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2329 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2330 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2331 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2332 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2333 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2334 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2335 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2336 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2337 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2338 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2340 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2342 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2343 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2344 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2345 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2346 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2347 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2348 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2349 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2350 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2351 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2352 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2354 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2359 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2360 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2361 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2362 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2363 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2364 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2365 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2367 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2368 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2369 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2370 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2371 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2372 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2373 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2374 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2375 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2376 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2377 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2378 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2379 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2380 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2382 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2383 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2384 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2385 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2386 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2389 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2390 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2391 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2392 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2393 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2394 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2395 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2396 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2397 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2398 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2399 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2400 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2402 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2403 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2404 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2406 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2408 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2409 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2410 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2412 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2413 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2415 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2417 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2418 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2419 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2421 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2422 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2423 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2424 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2425 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2427 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2428 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2429 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2430 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2432 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2433 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2434 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2435 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2436 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2437 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2438 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2439 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2440 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2441 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2442 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2443 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2444 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2445 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2446 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2447 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2448 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2449 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2451 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2452 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2453 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2454 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2455 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2456 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2457 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2458 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2459 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2460 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2461 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2462 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2463 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2464 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2465 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2466 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2467 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2468 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2469 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2470 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2471 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2472 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2473 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2475 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2477 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2483 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2486 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2494 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2495 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2496 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2497 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2498 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2499 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2500 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2501 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2502 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2503 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2505 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2506 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2507 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2508 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2509 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2510 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2511 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2512 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2513 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2514 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2515 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2516 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2518 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2519 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2520 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2521 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2522 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2523 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2525 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2526 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2527 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2528 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2529 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2530 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2532 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2533 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2534 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2535 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2536 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2537 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2538 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2539 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2541 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2542 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2544 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2545 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2546 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2547 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2549 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2550 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2551 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2552 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2554 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2555 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2556 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2557 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2558 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2559 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2560 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2561 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2563 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2564 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2565 { "evmwsmiaa", VX
2566 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2568 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2569 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2570 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2571 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2573 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2574 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2575 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2576 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2578 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2579 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2580 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2581 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2583 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2585 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2586 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
