Lines Matching refs:rw
39 target_ulong address, int rw, int access_type)
48 target_ulong address, int rw, int access_type)
66 target_ulong address, int rw, int access_type)
94 if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
110 int rw, int access_type)
133 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
139 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
147 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
164 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
188 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
196 ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
203 address, rw, access_type, *physical, *prot, ret);
211 int rw, int tlb_error)
220 if (rw)
227 if (rw)
235 if (rw)
343 static inline int cpu_mips_tlb_refill(CPUState *env, target_ulong address, int rw ,
415 if (rw == 0 || (n ? (elo_odd & 4) != 0 : (elo_even & 4) != 0)) {
438 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
452 qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
453 __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
455 rw &= 1;
465 address, rw, access_type);
474 ret = cpu_mips_tlb_refill(env,address,rw,mmu_idx,is_softmmu);
478 raise_mmu_exception(env, address, rw, ret);
486 target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
493 rw &= 1;
498 address, rw, access_type);
500 raise_mmu_exception(env, address, rw, ret);
