Lines Matching defs:tlb
811 unsigned int tmp = env->tlb->nb_tlb;
832 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1076 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1129 /* If the ASID changes, flush qemu's TLB. */
1503 r4k_tlb_t *tlb;
1506 tlb = &env->tlb->mmu.r4k.tlb[idx];
1507 /* The qemu TLB is flushed when the ASID changes, so no need to
1509 if (tlb->G == 0 && tlb->ASID != ASID) {
1516 r4k_tlb_t *tlb;
1522 tlb = &env->tlb->mmu.r4k.tlb[idx];
1523 /* The qemu TLB is flushed when the ASID changes, so no need to
1525 if (tlb->G == 0 && tlb->ASID != ASID) {
1530 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1531 if (tlb->V0) {
1532 addr = tlb->VPN & ~mask;
1544 if (tlb->V1) {
1545 addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
1559 /* TLB management */
1562 /* Flush qemu's TLB and discard all shadowed entries. */
1568 r4k_tlb_t *tlb;
1571 tlb = &env->tlb->mmu.r4k.tlb[idx];
1572 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1574 tlb->VPN &= env->SEGMask;
1576 tlb->ASID = env->CP0_EntryHi & 0xFF;
1577 tlb->PageMask = env->CP0_PageMask;
1578 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1579 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1580 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1581 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1582 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1583 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1584 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1585 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1586 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1597 /* Do TLB load on behalf of Page Table Walk */
1608 r4k_tlb_t *tlb;
1614 * we do not need to flush tlb hash table.
1616 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
1617 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1619 VPN = tlb->VPN & ~mask;
1622 if (tlb->ASID == (env->CP0_EntryHi & 0xFF))
1624 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1625 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1626 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1627 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1628 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1629 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1630 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1631 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1636 /*flush all the tlb cache */
1639 r4k_invalidate_tlb(env, env->CP0_Index % env->tlb->nb_tlb);
1640 r4k_fill_tlb(env->CP0_Index % env->tlb->nb_tlb);
1653 r4k_tlb_t *tlb;
1663 for (i = 0; i < env->tlb->nb_tlb; i++) {
1664 tlb = &env->tlb->mmu.r4k.tlb[i];
1666 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1668 VPN = tlb->VPN & ~mask;
1670 if (unlikely((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag)) {
1671 /* TLB match */
1676 if (i == env->tlb->nb_tlb) {
1686 r4k_tlb_t *tlb;
1690 tlb = &env->tlb->mmu.r4k.tlb[env->CP0_Index % env->tlb->nb_tlb];
1692 /* If this will change the current ASID, flush qemu's TLB. */
1693 if (ASID != tlb->ASID)
1696 /*flush all the tlb cache */
1699 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1700 env->CP0_PageMask = tlb->PageMask;
1701 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1702 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1703 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1704 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1709 env->tlb->helper_tlbwi();
1714 env->tlb->helper_tlbwr();
1719 env->tlb->helper_tlbp();
1724 env->tlb->helper_tlbr();
1960 /* the page is not in the TLB : fill it */
