Lines Matching refs:ori
182 // specially coded on MIPS means that it is a lui/ori instruction, and that is
574 return opcode == ORI;
1257 void Assembler::ori(Register rt, Register rs, int32_t j) {
1259 GenInstrImmediate(ORI, rs, rt, j);
1344 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
2101 ori(at, at, (imm32 & kImm16Mask));
2127 // Interpret 2 instructions generated by li: lui/ori
2128 if ((GetOpcodeField(instr1) == LUI) && (GetOpcodeField(instr2) == ORI)) {
2149 // On Mips, a target address is stored in a lui/ori instruction pair, each
2165 CHECK((GetOpcodeField(instr1) == LUI && GetOpcodeField(instr2) == ORI));
2168 // Must use 2 instructions to insure patchable code => just use lui and ori.
2170 // ori rt rt, lower-16.
2172 *(p+1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
2231 // JALR rs reg is the rt reg specified in the ORI instruction.
2243 // JR 'rs' reg is the 'rt' reg specified in the ORI instruction (instr2).
2254 // Address pc points to lui/ori instructions.
2266 ASSERT(GetOpcodeField(instr2) == ORI);
2274 ASSERT(GetOpcodeField(instr2) == ORI);
