Lines Matching refs:Ain
611 i->Ain.Imm64.imm64 = imm64;
612 i->Ain.Imm64.dst = dst;
618 i->Ain.Alu64R.op = op;
619 i->Ain.Alu64R.src = src;
620 i->Ain.Alu64R.dst = dst;
626 i->Ain.Alu64M.op = op;
627 i->Ain.Alu64M.src = src;
628 i->Ain.Alu64M.dst = dst;
635 i->Ain.Sh64.op = op;
636 i->Ain.Sh64.src = src;
637 i->Ain.Sh64.dst = dst;
643 i->Ain.Test64.imm32 = imm32;
644 i->Ain.Test64.dst = dst;
650 i->Ain.Unary64.op = op;
651 i->Ain.Unary64.dst = dst;
657 i->Ain.Lea64.am = am;
658 i->Ain.Lea64.dst = dst;
664 i->Ain.Alu32R.op = op;
665 i->Ain.Alu32R.src = src;
666 i->Ain.Alu32R.dst = dst;
677 i->Ain.MulL.syned = syned;
678 i->Ain.MulL.src = src;
684 i->Ain.Div.syned = syned;
685 i->Ain.Div.sz = sz;
686 i->Ain.Div.src = src;
693 i->Ain.Push.src = src;
699 i->Ain.Call.cond = cond;
700 i->Ain.Call.target = target;
701 i->Ain.Call.regparms = regparms;
710 i->Ain.XDirect.dstGA = dstGA;
711 i->Ain.XDirect.amRIP = amRIP;
712 i->Ain.XDirect.cond = cond;
713 i->Ain.XDirect.toFastEP = toFastEP;
720 i->Ain.XIndir.dstGA = dstGA;
721 i->Ain.XIndir.amRIP = amRIP;
722 i->Ain.XIndir.cond = cond;
729 i->Ain.XAssisted.dstGA = dstGA;
730 i->Ain.XAssisted.amRIP = amRIP;
731 i->Ain.XAssisted.cond = cond;
732 i->Ain.XAssisted.jk = jk;
739 i->Ain.CMov64.cond = cond;
740 i->Ain.CMov64.src = src;
741 i->Ain.CMov64.dst = dst;
748 i->Ain.MovxLQ.syned = syned;
749 i->Ain.MovxLQ.src = src;
750 i->Ain.MovxLQ.dst = dst;
757 i->Ain.LoadEX.szSmall = szSmall;
758 i->Ain.LoadEX.syned = syned;
759 i->Ain.LoadEX.src = src;
760 i->Ain.LoadEX.dst = dst;
767 i->Ain.Store.sz = sz;
768 i->Ain.Store.src = src;
769 i->Ain.Store.dst = dst;
776 i->Ain.Set64.cond = cond;
777 i->Ain.Set64.dst = dst;
783 i->Ain.Bsfr64.isFwds = isFwds;
784 i->Ain.Bsfr64.src = src;
785 i->Ain.Bsfr64.dst = dst;
796 i->Ain.ACAS.addr = addr;
797 i->Ain.ACAS.sz = sz;
804 i->Ain.DACAS.addr = addr;
805 i->Ain.DACAS.sz = sz;
814 i->Ain.A87Free.nregs = nregs;
822 i->Ain.A87PushPop.addr = addr;
823 i->Ain.A87PushPop.isPush = isPush;
824 i->Ain.A87PushPop.szB = szB;
832 i->Ain.A87FpOp.op = op;
839 i->Ain.A87LdCW.addr = addr;
846 i->Ain.A87StSW.addr = addr;
852 i->Ain.LdMXCSR.addr = addr;
858 i->Ain.SseUComIS.sz = toUChar(sz);
859 i->Ain.SseUComIS.srcL = srcL;
860 i->Ain.SseUComIS.srcR = srcR;
861 i->Ain.SseUComIS.dst = dst;
868 i->Ain.SseSI2SF.szS = toUChar(szS);
869 i->Ain.SseSI2SF.szD = toUChar(szD);
870 i->Ain.SseSI2SF.src = src;
871 i->Ain.SseSI2SF.dst = dst;
879 i->Ain.SseSF2SI.szS = toUChar(szS);
880 i->Ain.SseSF2SI.szD = toUChar(szD);
881 i->Ain.SseSF2SI.src = src;
882 i->Ain.SseSF2SI.dst = dst;
891 i->Ain.SseSDSS.from64 = from64;
892 i->Ain.SseSDSS.src = src;
893 i->Ain.SseSDSS.dst = dst;
900 i->Ain.SseLdSt.isLoad = isLoad;
901 i->Ain.SseLdSt.sz = toUChar(sz);
902 i->Ain.SseLdSt.reg = reg;
903 i->Ain.SseLdSt.addr = addr;
911 i->Ain.SseLdzLO.sz = sz;
912 i->Ain.SseLdzLO.reg = reg;
913 i->Ain.SseLdzLO.addr = addr;
920 i->Ain.Sse32Fx4.op = op;
921 i->Ain.Sse32Fx4.src = src;
922 i->Ain.Sse32Fx4.dst = dst;
929 i->Ain.Sse32FLo.op = op;
930 i->Ain.Sse32FLo.src = src;
931 i->Ain.Sse32FLo.dst = dst;
938 i->Ain.Sse64Fx2.op = op;
939 i->Ain.Sse64Fx2.src = src;
940 i->Ain.Sse64Fx2.dst = dst;
947 i->Ain.Sse64FLo.op = op;
948 i->Ain.Sse64FLo.src = src;
949 i->Ain.Sse64FLo.dst = dst;
956 i->Ain.SseReRg.op = op;
957 i->Ain.SseReRg.src = re;
958 i->Ain.SseReRg.dst = rg;
964 i->Ain.SseCMov.cond = cond;
965 i->Ain.SseCMov.src = src;
966 i->Ain.SseCMov.dst = dst;
973 i->Ain.SseShuf.order = order;
974 i->Ain.SseShuf.src = src;
975 i->Ain.SseShuf.dst = dst;
983 //uu i->Ain.AvxLdSt.isLoad = isLoad;
984 //uu i->Ain.AvxLdSt.reg = reg;
985 //uu i->Ain.AvxLdSt.addr = addr;
991 //uu i->Ain.AvxReRg.op = op;
992 //uu i->Ain.AvxReRg.src = re;
993 //uu i->Ain.AvxReRg.dst = rg;
1000 i->Ain.EvCheck.amCounter = amCounter;
1001 i->Ain.EvCheck.amFailAddr = amFailAddr;
1015 vex_printf("movabsq $0x%llx,", i->Ain.Imm64.imm64);
1016 ppHRegAMD64(i->Ain.Imm64.dst);
1019 vex_printf("%sq ", showAMD64AluOp(i->Ain.Alu64R.op));
1020 Ain.Alu64R.src);
1022 ppHRegAMD64(i->Ain.Alu64R.dst);
1025 vex_printf("%sq ", showAMD64AluOp(i->Ain.Alu64M.op));
1026 ppAMD64RI(i->Ain.Alu64M.src);
1028 ppAMD64AMode(i->Ain.Alu64M.dst);
1031 vex_printf("%sq ", showAMD64ShiftOp(i->Ain.Sh64.op));
1032 if (i->Ain.Sh64.src == 0)
1035 vex_printf("$%d,", (Int)i->Ain.Sh64.src);
1036 ppHRegAMD64(i->Ain.Sh64.dst);
1039 vex_printf("testq $%d,", (Int)i->Ain.Test64.imm32);
1040 ppHRegAMD64(i->Ain.Test64.dst);
1043 vex_printf("%sq ", showAMD64UnaryOp(i->Ain.Unary64.op));
1044 ppHRegAMD64(i->Ain.Unary64.dst);
1048 ppAMD64AMode(i->Ain.Lea64.am);
1050 ppHRegAMD64(i->Ain.Lea64.dst);
1053 vex_printf("%sl ", showAMD64AluOp(i->Ain.Alu32R.op));
1054 ppAMD64RMI_lo32(i->Ain.Alu32R.src);
1056 ppHRegAMD64_lo32(i->Ain.Alu32R.dst);
1059 vex_printf("%cmulq ", i->Ain.MulL.syned ? 's' : 'u');
1060 ppAMD64RM(i->Ain.MulL.src);
1064 i->Ain.Div.syned ? 's' : 'u',
1065 showAMD64ScalarSz(i->Ain.Div.sz));
1066 ppAMD64RM(i->Ain.Div.src);
1070 ppAMD64RMI(i->Ain.Push.src);
1074 i->Ain.Call.cond==Acc_ALWAYS
1075 ? "" : showAMD64CondCode(i->Ain.Call.cond),
1076 i->Ain.Call.regparms );
1077 vex_printf("0x%llx", i->Ain.Call.target);
1083 showAMD64CondCode(i->Ain.XDirect.cond));
1084 vex_printf("movabsq $0x%llx,%%r11; ", i->Ain.XDirect.dstGA);
1086 ppAMD64AMode(i->Ain.XDirect.amRIP);
1089 i->Ain.XDirect.toFastEP ? "fast" : "slow");
1094 showAMD64CondCode(i->Ain.XIndir.cond));
1096 ppHRegAMD64(i->Ain.XIndir.dstGA);
1098 ppAMD64AMode(i->Ain.XIndir.amRIP);
1104 showAMD64CondCode(i->Ain.XAssisted.cond));
1106 ppHRegAMD64(i->Ain.XAssisted.dstGA);
1108 ppAMD64AMode(i->Ain.XAssisted.amRIP);
1110 (Int)i->Ain.XAssisted.jk);
1115 vex_printf("cmov%s ", showAMD64CondCode(i->Ain.CMov64.cond));
1116 ppAMD64RM(i->Ain.CMov64.src);
1118 ppHRegAMD64(i->Ain.CMov64.dst);
1121 vex_printf("mov%clq ", i->Ain.MovxLQ.syned ? 's' : 'z');
1122 ppHRegAMD64_lo32(i->Ain.MovxLQ.src);
1124 ppHRegAMD64(i->Ain.MovxLQ.dst);
1127 if (i->Ain.LoadEX.szSmall==4 && !i->Ain.LoadEX.syned) {
1129 ppAMD64AMode(i->Ain.LoadEX.src);
1131 ppHRegAMD64_lo32(i->Ain.LoadEX.dst);
1134 i->Ain.LoadEX.syned ? 's' : 'z',
1135 i->Ain.LoadEX.szSmall==1
1137 : (i->Ain.LoadEX.szSmall==2 ? 'w' : 'l'));
1138 ppAMD64AMode(i->Ain.LoadEX.src);
1140 ppHRegAMD64(i->Ain.LoadEX.dst);
1144 vex_printf("mov%c ", i->Ain.Store.sz==1 ? 'b'
1145 : (i->Ain.Store.sz==2 ? 'w' : 'l'));
1146 ppHRegAMD64(i->Ain.Store.src);
1148 ppAMD64AMode(i->Ain.Store.dst);
1151 vex_printf("setq%s ", showAMD64CondCode(i->Ain.Set64.cond));
1152 ppHRegAMD64(i->Ain.Set64.dst);
1155 vex_printf("bs%cq ", i->Ain.Bsfr64.isFwds ? 'f' : 'r');
1156 ppHRegAMD64(i->Ain.Bsfr64.src);
1158 ppHRegAMD64(i->Ain.Bsfr64.dst);
1165 i->Ain.ACAS.sz==1 ? 'b' : i->Ain.ACAS.sz==2 ? 'w'
1166 : i->Ain.ACAS.sz==4 ? 'l' : 'q' );
1168 ppAMD64AMode(i->Ain.ACAS.addr);
1172 (Int)(2 * i->Ain.DACAS.sz));
1173 ppAMD64AMode(i->Ain.DACAS.addr);
1176 vex_printf("ffree %%st(7..%d)", 8 - i->Ain.A87Free.nregs );
1179 vex_printf(i->Ain.A87PushPop.isPush ? "fld%c " : "fstp%c ",
1180 i->Ain.A87PushPop.szB == 4 ? 's' : 'l');
1181 ppAMD64AMode(i->Ain.A87PushPop.addr);
1184 vex_printf("f%s", showA87FpOp(i->Ain.A87FpOp.op));
1188 ppAMD64AMode(i->Ain.A87LdCW.addr);
1192 ppAMD64AMode(i->Ain.A87StSW.addr);
1196 ppAMD64AMode(i->Ain.LdMXCSR.addr);
1199 vex_printf("ucomis%s ", i->Ain.SseUComIS.sz==4 ? "s" : "d");
1200 ppHRegAMD64(i->Ain.SseUComIS.srcL);
1202 ppHRegAMD64(i->Ain.SseUComIS.srcR);
1204 ppHRegAMD64(i->Ain.SseUComIS.dst);
1207 vex_printf("cvtsi2s%s ", i->Ain.SseSI2SF.szD==4 ? "s" : "d");
1208 (i->Ain.SseSI2SF.szS==4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1209 (i->Ain.SseSI2SF.src);
1211 ppHRegAMD64(i->Ain.SseSI2SF.dst);
1214 vex_printf("cvts%s2si ", i->Ain.SseSF2SI.szS==4 ? "s" : "d");
1215 ppHRegAMD64(i->Ain.SseSF2SI.src);
1217 (i->Ain.SseSF2SI.szD==4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1218 (i->Ain.SseSF2SI.dst);
1221 vex_printf(i->Ain.SseSDSS.from64 ? "cvtsd2ss " : "cvtss2sd ");
1222 ppHRegAMD64(i->Ain.SseSDSS.src);
1224 ppHRegAMD64(i->Ain.SseSDSS.dst);
1227 switch (i->Ain.SseLdSt.sz) {
1233 if (i->Ain.SseLdSt.isLoad) {
1234 ppAMD64AMode(i->Ain.SseLdSt.addr);
1236 ppHRegAMD64(i->Ain.SseLdSt.reg);
1238 ppHRegAMD64(i->Ain.SseLdSt.reg);
1240 ppAMD64AMode(i->Ain.SseLdSt.addr);
1244 vex_printf("movs%s ", i->Ain.SseLdzLO.sz==4 ? "s" : "d");
1245 ppAMD64AMode(i->Ain.SseLdzLO.addr);
1247 ppHRegAMD64(i->Ain.SseLdzLO.reg);
1250 vex_printf("%sps ", showAMD64SseOp(i->Ain.Sse32Fx4.op));
1251 ppHRegAMD64(i->Ain.Sse32Fx4.src);
1253 ppHRegAMD64(i->Ain.Sse32Fx4.dst);
1256 vex_printf("%sss ", showAMD64SseOp(i->Ain.Sse32FLo.op));
1257 ppHRegAMD64(i->Ain.Sse32FLo.src);
1259 ppHRegAMD64(i->Ain.Sse32FLo.dst);
1262 vex_printf("%spd ", showAMD64SseOp(i->Ain.Sse64Fx2.op));
1263 ppHRegAMD64(i->Ain.Sse64Fx2.src);
1265 ppHRegAMD64(i->Ain.Sse64Fx2.dst);
1268 vex_printf("%ssd ", showAMD64SseOp(i->Ain.Sse64FLo.op));
1269 ppHRegAMD64(i->Ain.Sse64FLo.src);
1271 ppHRegAMD64(i->Ain.Sse64FLo.dst);
1274 vex_printf("%s ", showAMD64SseOp(i->Ain.SseReRg.op));
1275 ppHRegAMD64(i->Ain.SseReRg.src);
1277 ppHRegAMD64(i->Ain.SseReRg.dst);
1280 vex_printf("cmov%s ", showAMD64CondCode(i->Ain.SseCMov.cond));
1281 ppHRegAMD64(i->Ain.SseCMov.src);
1283 ppHRegAMD64(i->Ain.SseCMov.dst);
1286 vex_printf("pshufd $0x%x,", i->Ain.SseShuf.order);
1287 ppHRegAMD64(i->Ain.SseShuf.src);
1289 ppHRegAMD64(i->Ain.SseShuf.dst);
1293 //uu if (i->Ain.AvxLdSt.isLoad) {
1294 //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
1296 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1298 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1300 //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
1304 //uu vex_printf("v%s ", showAMD64SseOp(i->Ain.SseReRg.op));
1305 //uu ppHRegAMD64(i->Ain.AvxReRg.src);
1307 //uu ppHRegAMD64(i->Ain.AvxReRg.dst);
1311 ppAMD64AMode(i->Ain.EvCheck.amCounter);
1313 ppAMD64AMode(i->Ain.EvCheck.amFailAddr);
1333 addHRegUse(u, HRmWrite, i->Ain.Imm64.dst);
1336 addRegUsage_AMD64RMI(u, i->Ain.Alu64R.src);
1337 if (i->Ain.Alu64R.op == Aalu_MOV) {
1338 addHRegUse(u, HRmWrite, i->Ain.Alu64R.dst);
1341 if (i->Ain.Alu64R.op == Aalu_CMP) {
1342 addHRegUse(u, HRmRead, i->Ain.Alu64R.dst);
1345 addHRegUse(u, HRmModify, i->Ain.Alu64R.dst);
1348 addRegUsage_AMD64RI(u, i->Ain.Alu64M.src);
1349 addRegUsage_AMD64AMode(u, i->Ain.Alu64M.dst);
1352 addHRegUse(u, HRmModify, i->Ain.Sh64.dst);
1353 if (i->Ain.Sh64.src == 0)
1357 addHRegUse(u, HRmRead, i->Ain.Test64.dst);
1360 addHRegUse(u, HRmModify, i->Ain.Unary64.dst);
1363 addRegUsage_AMD64AMode(u, i->Ain.Lea64.am);
1364 addHRegUse(u, HRmWrite, i->Ain.Lea64.dst);
1367 vassert(i->Ain.Alu32R.op != Aalu_MOV);
1368 addRegUsage_AMD64RMI(u, i->Ain.Alu32R.src);
1369 if (i->Ain.Alu32R.op == Aalu_CMP) {
1370 addHRegUse(u, HRmRead, i->Ain.Alu32R.dst);
1373 addHRegUse(u, HRmModify, i->Ain.Alu32R.dst);
1376 addRegUsage_AMD64RM(u, i->Ain.MulL.src, HRmRead);
1381 addRegUsage_AMD64RM(u, i->Ain.Div.src, HRmRead);
1386 addRegUsage_AMD64RMI(u, i->Ain.Push.src);
1420 switch (i->Ain.Call.regparms) {
1446 addRegUsage_AMD64AMode(u, i->Ain.XDirect.amRIP);
1450 addHRegUse(u, HRmRead, i->Ain.XIndir.dstGA);
1451 addRegUsage_AMD64AMode(u, i->Ain.XIndir.amRIP);
1455 addHRegUse(u, HRmRead, i->Ain.XAssisted.dstGA);
1456 addRegUsage_AMD64AMode(u, i->Ain.XAssisted.amRIP);
1459 addRegUsage_AMD64RM(u, i->Ain.CMov64.src, HRmRead);
1460 addHRegUse(u, HRmModify, i->Ain.CMov64.dst);
1463 addHRegUse(u, HRmRead, i->Ain.MovxLQ.src);
1464 addHRegUse(u, HRmWrite, i->Ain.MovxLQ.dst);
1467 addRegUsage_AMD64AMode(u, i->Ain.LoadEX.src);
1468 addHRegUse(u, HRmWrite, i->Ain.LoadEX.dst);
1471 addHRegUse(u, HRmRead, i->Ain.Store.src);
1472 addRegUsage_AMD64AMode(u, i->Ain.Store.dst);
1475 addHRegUse(u, HRmWrite, i->Ain.Set64.dst);
1478 addHRegUse(u, HRmRead, i->Ain.Bsfr64.src);
1479 addHRegUse(u, HRmWrite, i->Ain.Bsfr64.dst);
1484 addRegUsage_AMD64AMode(u, i->Ain.ACAS.addr);
1489 addRegUsage_AMD64AMode(u, i->Ain.DACAS.addr);
1498 addRegUsage_AMD64AMode(u, i->Ain.A87PushPop.addr);
1503 addRegUsage_AMD64AMode(u, i->Ain.A87LdCW.addr);
1506 addRegUsage_AMD64AMode(u, i->Ain.A87StSW.addr);
1509 addRegUsage_AMD64AMode(u, i->Ain.LdMXCSR.addr);
1512 addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcL);
1513 addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcR);
1514 addHRegUse(u, HRmWrite, i->Ain.SseUComIS.dst);
1517 addHRegUse(u, HRmRead, i->Ain.SseSI2SF.src);
1518 addHRegUse(u, HRmWrite, i->Ain.SseSI2SF.dst);
1521 addHRegUse(u, HRmRead, i->Ain.SseSF2SI.src);
1522 addHRegUse(u, HRmWrite, i->Ain.SseSF2SI.dst);
1525 addHRegUse(u, HRmRead, i->Ain.SseSDSS.src);
1526 addHRegUse(u, HRmWrite, i->Ain.SseSDSS.dst);
1529 addRegUsage_AMD64AMode(u, i->Ain.SseLdSt.addr);
1530 addHRegUse(u, i->Ain.SseLdSt.isLoad ? HRmWrite : HRmRead,
1531 i->Ain.SseLdSt.reg);
1534 addRegUsage_AMD64AMode(u, i->Ain.SseLdzLO.addr);
1535 addHRegUse(u, HRmWrite, i->Ain.SseLdzLO.reg);
1538 vassert(i->Ain.Sse32Fx4.op != Asse_MOV);
1539 unary = toBool( i->Ain.Sse32Fx4.op == Asse_RCPF
1540 || i->Ain.Sse32Fx4.op == Asse_RSQRTF
1541 || i->Ain.Sse32Fx4.op == Asse_SQRTF );
1542 addHRegUse(u, HRmRead, i->Ain.Sse32Fx4.src);
1544 i->Ain.Sse32Fx4.dst);
1547 vassert(i->Ain.Sse32FLo.op != Asse_MOV);
1548 unary = toBool( i->Ain.Sse32FLo.op == Asse_RCPF
1549 || i->Ain.Sse32FLo.op == Asse_RSQRTF
1550 || i->Ain.Sse32FLo.op == Asse_SQRTF );
1551 addHRegUse(u, HRmRead, i->Ain.Sse32FLo.src);
1553 i->Ain.Sse32FLo.dst);
1556 vassert(i->Ain.Sse64Fx2.op != Asse_MOV);
1557 unary = toBool( i->Ain.Sse64Fx2.op == Asse_RCPF
1558 || i->Ain.Sse64Fx2.op == Asse_RSQRTF
1559 || i->Ain.Sse64Fx2.op == Asse_SQRTF );
1560 addHRegUse(u, HRmRead, i->Ain.Sse64Fx2.src);
1562 i->Ain.Sse64Fx2.dst);
1565 vassert(i->Ain.Sse64FLo.op != Asse_MOV);
1566 unary = toBool( i->Ain.Sse64FLo.op == Asse_RCPF
1567 || i->Ain.Sse64FLo.op == Asse_RSQRTF
1568 || i->Ain.Sse64FLo.op == Asse_SQRTF );
1569 addHRegUse(u, HRmRead, i->Ain.Sse64FLo.src);
1571 i->Ain.Sse64FLo.dst);
1574 if ( (i->Ain.SseReRg.op == Asse_XOR
1575 || i->Ain.SseReRg.op == Asse_CMPEQ32)
1576 && i->Ain.SseReRg.src == i->Ain.SseReRg.dst) {
1581 addHRegUse(u, HRmWrite, i->Ain.SseReRg.dst);
1583 addHRegUse(u, HRmRead, i->Ain.SseReRg.src);
1584 addHRegUse(u, i->Ain.SseReRg.op == Asse_MOV
1586 i->Ain.SseReRg.dst);
1590 addHRegUse(u, HRmRead, i->Ain.SseCMov.src);
1591 addHRegUse(u, HRmModify, i->Ain.SseCMov.dst);
1594 addHRegUse(u, HRmRead, i->Ain.SseShuf.src);
1595 addHRegUse(u, HRmWrite, i->Ain.SseShuf.dst);
1598 //uu addRegUsage_AMD64AMode(u, i->Ain.AvxLdSt.addr);
1599 //uu addHRegUse(u, i->Ain.AvxLdSt.isLoad ? HRmWrite : HRmRead,
1600 //uu i->Ain.AvxLdSt.reg);
1603 //uu if ( (i->Ain.AvxReRg.op == Asse_XOR
1604 //uu || i->Ain.AvxReRg.op == Asse_CMPEQ32)
1605 //uu && i->Ain.AvxReRg.src == i->Ain.AvxReRg.dst) {
1607 //uu addHRegUse(u, HRmWrite, i->Ain.AvxReRg.dst);
1609 //uu addHRegUse(u, HRmRead, i->Ain.AvxReRg.src);
1610 //uu addHRegUse(u, i->Ain.AvxReRg.op == Asse_MOV
1612 //uu i->Ain.AvxReRg.dst);
1618 addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amCounter);
1619 addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amFailAddr);
1641 mapReg(m, &i->Ain.Imm64.dst);
1644 mapRegs_AMD64RMI(m, i->Ain.Alu64R.src);
1645 mapReg(m, &i->Ain.Alu64R.dst);
1648 mapRegs_AMD64RI(m, i->Ain.Alu64M.src);
1649 mapRegs_AMD64AMode(m, i->Ain.Alu64M.dst);
1652 mapReg(m, &i->Ain.Sh64.dst);
1655 mapReg(m, &i->Ain.Test64.dst);
1658 mapReg(m, &i->Ain.Unary64.dst);
1661 mapRegs_AMD64AMode(m, i->Ain.Lea64.am);
1662 mapReg(m, &i->Ain.Lea64.dst);
1665 mapRegs_AMD64RMI(m, i->Ain.Alu32R.src);
1666 mapReg(m, &i->Ain.Alu32R.dst);
1669 mapRegs_AMD64RM(m, i->Ain.MulL.src);
1672 mapRegs_AMD64RM(m, i->Ain.Div.src);
1675 mapRegs_AMD64RMI(m, i->Ain.Push.src);
1680 mapRegs_AMD64AMode(m, i->Ain.XDirect.amRIP);
1683 mapReg(m, &i->Ain.XIndir.dstGA);
1684 mapRegs_AMD64AMode(m, i->Ain.XIndir.amRIP);
1687 mapReg(m, &i->Ain.XAssisted.dstGA);
1688 mapRegs_AMD64AMode(m, i->Ain.XAssisted.amRIP);
1691 mapRegs_AMD64RM(m, i->Ain.CMov64.src);
1692 mapReg(m, &i->Ain.CMov64.dst);
1695 mapReg(m, &i->Ain.MovxLQ.src);
1696 mapReg(m, &i->Ain.MovxLQ.dst);
1699 mapRegs_AMD64AMode(m, i->Ain.LoadEX.src);
1700 mapReg(m, &i->Ain.LoadEX.dst);
1703 mapReg(m, &i->Ain.Store.src);
1704 mapRegs_AMD64AMode(m, i->Ain.Store.dst);
1707 mapReg(m, &i->Ain.Set64.dst);
1710 mapReg(m, &i->Ain.Bsfr64.src);
1711 mapReg(m, &i->Ain.Bsfr64.dst);
1716 mapRegs_AMD64AMode(m, i->Ain.ACAS.addr);
1719 mapRegs_AMD64AMode(m, i->Ain.DACAS.addr);
1724 mapRegs_AMD64AMode(m, i->Ain.A87PushPop.addr);
1729 mapRegs_AMD64AMode(m, i->Ain.A87LdCW.addr);
1732 mapRegs_AMD64AMode(m, i->Ain.A87StSW.addr);
1735 mapRegs_AMD64AMode(m, i->Ain.LdMXCSR.addr);
1738 mapReg(m, &i->Ain.SseUComIS.srcL);
1739 mapReg(m, &i->Ain.SseUComIS.srcR);
1740 mapReg(m, &i->Ain.SseUComIS.dst);
1743 mapReg(m, &i->Ain.SseSI2SF.src);
1744 mapReg(m, &i->Ain.SseSI2SF.dst);
1747 mapReg(m, &i->Ain.SseSF2SI.src);
1748 mapReg(m, &i->Ain.SseSF2SI.dst);
1751 mapReg(m, &i->Ain.SseSDSS.src);
1752 mapReg(m, &i->Ain.SseSDSS.dst);
1755 mapReg(m, &i->Ain.SseLdSt.reg);
1756 mapRegs_AMD64AMode(m, i->Ain.SseLdSt.addr);
1759 mapReg(m, &i->Ain.SseLdzLO.reg);
1760 mapRegs_AMD64AMode(m, i->Ain.SseLdzLO.addr);
1763 mapReg(m, &i->Ain.Sse32Fx4.src);
1764 mapReg(m, &i->Ain.Sse32Fx4.dst);
1767 mapReg(m, &i->Ain.Sse32FLo.src);
1768 mapReg(m, &i->Ain.Sse32FLo.dst);
1771 mapReg(m, &i->Ain.Sse64Fx2.src);
1772 mapReg(m, &i->Ain.Sse64Fx2.dst);
1775 mapReg(m, &i->Ain.Sse64FLo.src);
1776 mapReg(m, &i->Ain.Sse64FLo.dst);
1779 mapReg(m, &i->Ain.SseReRg.src);
1780 mapReg(m, &i->Ain.SseReRg.dst);
1783 mapReg(m, &i->Ain.SseCMov.src);
1784 mapReg(m, &i->Ain.SseCMov.dst);
1787 mapReg(m, &i->Ain.SseShuf.src);
1788 mapReg(m, &i->Ain.SseShuf.dst);
1791 //uu mapReg(m, &i->Ain.AvxLdSt.reg);
1792 //uu mapRegs_AMD64AMode(m, i->Ain.AvxLdSt.addr);
1795 //uu mapReg(m, &i->Ain.AvxReRg.src);
1796 //uu mapReg(m, &i->Ain.AvxReRg.dst);
1801 mapRegs_AMD64AMode(m, i->Ain.EvCheck.amCounter);
1802 mapRegs_AMD64AMode(m, i->Ain.EvCheck.amFailAddr);
1822 if (i->Ain.Alu64R.op != Aalu_MOV)
1824 if (i->Ain.Alu64R.src->tag != Armi_Reg)
1826 *src = i->Ain.Alu64R.src->Armi.Reg.reg;
1827 *dst = i->Ain.Alu64R.dst;
1831 if (i->Ain.SseReRg.op != Asse_MOV)
1833 *src = i->Ain.SseReRg.src;
1834 *dst = i->Ain.SseReRg.dst;
1838 //uu if (i->Ain.AvxReRg.op != Asse_MOV)
1840 //uu *src = i->Ain.AvxReRg.src;
1841 //uu *dst = i->Ain.AvxReRg.dst;
2286 if (i->Ain.Imm64.imm64 <= 0xFFFFFULL) {
2291 if (1 & iregBit3(i->Ain.Imm64.dst))
2293 *p++ = 0xB8 + iregBits210(i->Ain.Imm64.dst);
2294 p = emit32(p, (UInt)i->Ain.Imm64.imm64);
2296 *p++ = toUChar(0x48 + (1 & iregBit3(i->Ain.Imm64.dst)));
2297 *p++ = toUChar(0xB8 + iregBits210(i->Ain.Imm64.dst));
2298 p = emit64(p, i->Ain.Imm64.imm64);
2304 if (i->Ain.Alu64R.op == Aalu_MOV) {
2305 switch (i->Ain.Alu64R.src->tag) {
2307 if (0 == (i->Ain.Alu64R.src->Armi.Imm.imm32 & ~0xFFFFF)) {
2317 if (1 & iregBit3(i->Ain.Alu64R.dst))
2319 *p++ = 0xB8 + iregBits210(i->Ain.Alu64R.dst);
2320 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2322 *p++ = toUChar(0x48 + (1 & iregBit3(i->Ain.Alu64R.dst)));
2324 *p++ = toUChar(0xC0 + iregBits210(i->Ain.Alu64R.dst));
2325 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2329 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2330 i->Ain.Alu64R.dst );
2332 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2333 i->Ain.Alu64R.dst);
2336 *p++ = rexAMode_M(i->Ain.Alu64R.dst,
2337 i->Ain.Alu64R.src->Armi.Mem.am);
2339 p = doAMode_M(p, i->Ain.Alu64R.dst,
2340 i->Ain.Alu64R.src->Armi.Mem.am);
2347 if (i->Ain.Alu64R.op == Aalu_MUL) {
2348 switch (i->Ain.Alu64R.src->tag) {
2350 *p++ = rexAMode_R( i->Ain.Alu64R.dst,
2351 i->Ain.Alu64R.src->Armi.Reg.reg);
2354 p = doAMode_R(p, i->Ain.Alu64R.dst,
2355 i->Ain.Alu64R.src->Armi.Reg.reg);
2358 *p++ = rexAMode_M(i->Ain.Alu64R.dst,
2359 i->Ain.Alu64R.src->Armi.Mem.am);
2362 p = doAMode_M(p, i->Ain.Alu64R.dst,
2363 i->Ain.Alu64R.src->Armi.Mem.am);
2366 if (fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2367 *p++ = rexAMode_R(i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2369 p = doAMode_R(p, i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2370 *p++ = toUChar(0xFF & i->Ain.Alu64R.src->Armi.Imm.imm32);
2372 *p++ = rexAMode_R(i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2374 p = doAMode_R(p, i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2375 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2384 switch (i->Ain.Alu64R.op) {
2403 switch (i->Ain.Alu64R.src->tag) {
2405 if (i->Ain.Alu64R.dst == hregAMD64_RAX()
2406 && !fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2409 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2411 if (fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2412 *p++ = rexAMode_R( fake(0), i->Ain.Alu64R.dst );
2414 p = doAMode_R(p, fake(subopc_imm), i->Ain.Alu64R.dst);
2415 *p++ = toUChar(0xFF & i->Ain.Alu64R.src->Armi.Imm.imm32);
2417 *p++ = rexAMode_R( fake(0), i->Ain.Alu64R.dst);
2419 p = doAMode_R(p, fake(subopc_imm), i->Ain.Alu64R.dst);
2420 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2424 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2425 i->Ain.Alu64R.dst);
2427 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2428 i->Ain.Alu64R.dst);
2431 *p++ = rexAMode_M( i->Ain.Alu64R.dst,
2432 i->Ain.Alu64R.src->Armi.Mem.am);
2434 p = doAMode_M(p, i->Ain.Alu64R.dst,
2435 i->Ain.Alu64R.src->Armi.Mem.am);
2444 if (i->Ain.Alu64M.op == Aalu_MOV) {
2445 switch (i->Ain.Alu64M.src->tag) {
2447 *p++ = rexAMode_M(i->Ain.Alu64M.src->Ari.Reg.reg,
2448 i->Ain.Alu64M.dst);
2450 p = doAMode_M(p, i->Ain.Alu64M.src->Ari.Reg.reg,
2451 i->Ain.Alu64M.dst);
2454 *p++ = rexAMode_M(fake(0), i->Ain.Alu64M.dst);
2456 p = doAMode_M(p, fake(0), i->Ain.Alu64M.dst);
2457 p = emit32(p, i->Ain.Alu64M.src->Ari.Imm.imm32);
2467 switch (i->Ain.Sh64.op) {
2473 if (i->Ain.Sh64.src == 0) {
2474 *p++ = rexAMode_R(fake(0), i->Ain.Sh64.dst);
2476 p = doAMode_R(p, fake(subopc), i->Ain.Sh64.dst);
2479 *p++ = rexAMode_R(fake(0), i->Ain.Sh64.dst);
2481 p = doAMode_R(p, fake(subopc), i->Ain.Sh64.dst);
2482 *p++ = (UChar)(i->Ain.Sh64.src);
2489 *p++ = rexAMode_R(fake(0), i->Ain.Test64.dst);
2491 p = doAMode_R(p, fake(0), i->Ain.Test64.dst);
2492 p = emit32(p, i->Ain.Test64.imm32);
2496 if (i->Ain.Unary64.op == Aun_NOT) {
2497 *p++ = rexAMode_R(fake(0), i->Ain.Unary64.dst);
2499 p = doAMode_R(p, fake(2), i->Ain.Unary64.dst);
2502 if (i->Ain.Unary64.op == Aun_NEG) {
2503 *p++ = rexAMode_R(fake(0), i->Ain.Unary64.dst);
2505 p = doAMode_R(p, fake(3), i->Ain.Unary64.dst);
2511 *p++ = rexAMode_M(i->Ain.Lea64.dst, i->Ain.Lea64.am);
2513 p = doAMode_M(p, i->Ain.Lea64.dst, i->Ain.Lea64.am);
2519 switch (i->Ain.Alu32R.op) {
2534 switch (i->Ain.Alu32R.src->tag) {
2536 if (i->Ain.Alu32R.dst == hregAMD64_RAX()
2537 && !fits8bits(i->Ain.Alu32R.src->Armi.Imm.imm32)) {
2540 p = emit32(p, i->Ain.Alu32R.src->Armi.Imm.imm32);
2542 if (fits8bits(i->Ain.Alu32R.src->Armi.Imm.imm32)) {
2543 rex = clearWBit( rexAMode_R( fake(0), i->Ain.Alu32R.dst ) );
2546 p = doAMode_R(p, fake(subopc_imm), i->Ain.Alu32R.dst);
2547 *p++ = toUChar(0xFF & i->Ain.Alu32R.src->Armi.Imm.imm32);
2549 rex = clearWBit( rexAMode_R( fake(0), i->Ain.Alu32R.dst) );
2552 p = doAMode_R(p, fake(subopc_imm), i->Ain.Alu32R.dst);
2553 p = emit32(p, i->Ain.Alu32R.src->Armi.Imm.imm32);
2558 rexAMode_R( i->Ain.Alu32R.src->Armi.Reg.reg,
2559 i->Ain.Alu32R.dst) );
2562 p = doAMode_R(p, i->Ain.Alu32R.src->Armi.Reg.reg,
2563 i->Ain.Alu32R.dst);
2567 rexAMode_M( i->Ain.Alu32R.dst,
2568 i->Ain.Alu32R.src->Armi.Mem.am) );
2571 p = doAMode_M(p, i->Ain.Alu32R.dst,
2572 i->Ain.Alu32R.src->Armi.Mem.am);
2580 subopc = i->Ain.MulL.syned ? 5 : 4;
2581 switch (i->Ain.MulL.src->tag) {
2584 i->Ain.MulL.src->Arm.Mem.am);
2587 i->Ain.MulL.src->Arm.Mem.am);
2591 i->Ain.MulL.src->Arm.Reg.reg);
2594 i->Ain.MulL.src->Arm.Reg.reg);
2602 subopc = i->Ain.Div.syned ? 7 : 6;
2603 if (i->Ain.Div.sz == 4) {
2604 switch (i->Ain.Div.src->tag) {
2610 i->Ain.Div.src->Arm.Mem.am);
2614 rexAMode_R( fake(0), i->Ain.Div.src->Arm.Reg.reg));
2617 i->Ain.Div.src->Arm.Reg.reg);
2623 if (i->Ain.Div.sz == 8) {
2624 switch (i->Ain.Div.src->tag) {
2627 i->Ain.Div.src->Arm.Mem.am);
2630 i->Ain.Div.src->Arm.Mem.am);
2634 i->Ain.Div.src->Arm.Reg.reg);
2637 i->Ain.Div.src->Arm.Reg.reg);
2646 switch (i->Ain.Push.src->tag) {
2649 rexAMode_M(fake(0), i->Ain.Push.src->Armi.Mem.am));
2651 p = doAMode_M(p, fake(6), i->Ain.Push.src->Armi.Mem.am);
2655 p = emit32(p, i->Ain.Push.src->Armi.Imm.imm32);
2658 *p++ = toUChar(0x40 + (1 & iregBit3(i->Ain.Push.src->Armi.Reg.reg)));
2659 *p++ = toUChar(0x50 + iregBits210(i->Ain.Push.src->Armi.Reg.reg));
2671 Bool shortImm = fitsIn32Bits(i->Ain.Call.target);
2672 if (i->Ain.Call.cond != Acc_ALWAYS) {
2673 *p++ = toUChar(0x70 + (0xF & (i->Ain.Call.cond ^ 1)));
2682 p = emit32(p, (UInt)i->Ain.Call.target);
2687 p = emit64(p, i->Ain.Call.target);
2712 if (i->Ain.XDirect.cond != Acc_ALWAYS) {
2714 *p++ = toUChar(0x70 + (0xF & (i->Ain.XDirect.cond ^ 1)));
2720 if (fitsIn32Bits(i->Ain.XDirect.dstGA)) {
2726 p = emit32(p, (UInt)i->Ain.XDirect.dstGA);
2731 p = emit64(p, i->Ain.XDirect.dstGA);
2735 *p++ = rexAMode_M(r11, i->Ain.XDirect.amRIP);
2737 p = doAMode_M(p, r11, i->Ain.XDirect.amRIP);
2748 = i->Ain.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
2758 if (i->Ain.XDirect.cond != Acc_ALWAYS) {
2780 if (i->Ain.XIndir.cond != Acc_ALWAYS) {
2782 *p++ = toUChar(0x70 + (0xF & (i->Ain.XIndir.cond ^ 1)));
2788 *p++ = rexAMode_M(i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
2790 p = doAMode_M(p, i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
2813 if (i->Ain.XIndir.cond != Acc_ALWAYS) {
2827 if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
2829 *p++ = toUChar(0x70 + (0xF & (i->Ain.XAssisted.cond ^ 1)));
2835 *p++ = rexAMode_M(i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
2837 p = doAMode_M(p, i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
2842 switch (i->Ain.XAssisted.jk) {
2860 ppIRJumpKind(i->Ain.XAssisted.jk);
2876 if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
2885 vassert(i->Ain.CMov64.cond != Acc_ALWAYS);
2886 if (i->Ain.CMov64.src->tag == Arm_Reg) {
2887 *p++ = rexAMode_R(i->Ain.CMov64.dst, i->Ain.CMov64.src->Arm.Reg.reg);
2889 *p++ = toUChar(0x40 + (0xF & i->Ain.CMov64.cond));
2890 p = doAMode_R(p, i->Ain.CMov64.dst, i->Ain.CMov64.src->Arm.Reg.reg);
2893 if (i->Ain.CMov64.src->tag == Arm_Mem) {
2894 *p++ = rexAMode_M(i->Ain.CMov64.dst, i->Ain.CMov64.src->Arm.Mem.am);
2896 *p++ = toUChar(0x40 + (0xF & i->Ain.CMov64.cond));
2897 p = doAMode_M(p, i->Ain.CMov64.dst, i->Ain.CMov64.src->Arm.Mem.am);
2905 if (i->Ain.MovxLQ.syned) {
2907 *p++ = rexAMode_R(i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src);
2909 p = doAMode_R(p, i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src);
2914 rexAMode_R(i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst));
2916 p = doAMode_R(p, i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst);
2921 if (i->Ain.LoadEX.szSmall == 1 && !i->Ain.LoadEX.syned) {
2923 *p++ = rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
2926 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
2929 if (i->Ain.LoadEX.szSmall == 2 && !i->Ain.LoadEX.syned) {
2931 *p++ = rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
2934 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
2937 if (i->Ain.LoadEX.szSmall == 4 && !i->Ain.LoadEX.syned) {
2944 rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src));
2946 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
2957 reg = iregBits3210(i->Ain.Set64.dst);
2970 *p++ = toUChar(0x90 + (0x0F & i->Ain.Set64.cond));
2975 *p++ = rexAMode_R(i->Ain.Bsfr64.dst, i->Ain.Bsfr64.src);
2977 if (i->Ain.Bsfr64.isFwds) {
2982 p = doAMode_R(p, i->Ain.Bsfr64.dst, i->Ain.Bsfr64.src);
2993 if (i->Ain.ACAS.sz == 2) *p++ = 0x66;
2999 rex = rexAMode_M( hregAMD64_RBX(), i->Ain.ACAS.addr );
3000 if (i->Ain.ACAS.sz != 8)
3005 if (i->Ain.ACAS.sz == 1) *p++ = 0xB0; else *p++ = 0xB1;
3006 p = doAMode_M(p, hregAMD64_RBX(), i->Ain.ACAS.addr);
3015 rex = rexAMode_M( fake(1), i->Ain.ACAS.addr );
3016 if (i->Ain.ACAS.sz != 8)
3021 p = doAMode_M(p, fake(1), i->Ain.DACAS.addr);
3025 vassert(i->Ain.A87Free.nregs > 0 && i->Ain.A87Free.nregs <= 7);
3026 for (j = 0; j < i->Ain.A87Free.nregs; j++) {
3032 vassert(i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4);
3033 if (i->Ain.A87PushPop.isPush) {
3036 rexAMode_M(fake(0), i->Ain.A87PushPop.addr) );
3037 *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;
3038 p = doAMode_M(p, fake(0)/*subopcode*/, i->Ain.A87PushPop.addr);
3042 rexAMode_M(fake(3), i->Ain.A87PushPop.addr) );
3043 *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;
3044 p = doAMode_M(p, fake(3)/*subopcode*/, i->Ain.A87PushPop.addr);
3050 switch (i->Ain.A87FpOp.op) {
3069 rexAMode_M(fake(5), i->Ain.A87LdCW.addr) );
3071 p = doAMode_M(p, fake(5)/*subopcode*/, i->Ain.A87LdCW.addr);
3076 rexAMode_M(fake(7), i->Ain.A87StSW.addr) );
3078 p = doAMode_M(p, fake(7)/*subopcode*/, i->Ain.A87StSW.addr);
3082 if (i->Ain.Store.sz == 2) {
3088 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3090 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3093 if (i->Ain.Store.sz == 4) {
3094 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3096 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3099 if (i->Ain.Store.sz == 1) {
3103 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3105 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3111 *p++ = clearWBit(rexAMode_M( fake(0), i->Ain.LdMXCSR.addr));
3114 p = doAMode_M(p, fake(2)/*subopcode*/, i->Ain.LdMXCSR.addr);
3120 if (i->Ain.SseUComIS.sz == 8) {
3124 vassert(i->Ain.SseUComIS.sz == 4);
3127 rexAMode_R( vreg2ireg(i->Ain.SseUComIS.srcL),
3128 vreg2ireg(i->Ain.SseUComIS.srcR) ));
3131 p = doAMode_R(p, vreg2ireg(i->Ain.SseUComIS.srcL),
3132 vreg2ireg(i->Ain.SseUComIS.srcR) );
3136 *p++ = toUChar(0x40 + (1 & iregBit3(i->Ain.SseUComIS.dst)));
3137 *p++ = toUChar(0x58 + iregBits210(i->Ain.SseUComIS.dst));
3142 rex = rexAMode_R( vreg2ireg(i->Ain.SseSI2SF.dst),
3143 i->Ain.SseSI2SF.src );
3144 *p++ = toUChar(i->Ain.SseSI2SF.szD==4 ? 0xF3 : 0xF2);
3145 *p++ = toUChar(i->Ain.SseSI2SF.szS==4 ? clearWBit(rex) : rex);
3148 p = doAMode_R( p, vreg2ireg(i->Ain.SseSI2SF.dst),
3149 i->Ain.SseSI2SF.src );
3154 rex = rexAMode_R( i->Ain.SseSF2SI.dst,
3155 vreg2ireg(i->Ain.SseSF2SI.src) );
3156 *p++ = toUChar(i->Ain.SseSF2SI.szS==4 ? 0xF3 : 0xF2);
3157 *p++ = toUChar(i->Ain.SseSF2SI.szD==4 ? clearWBit(rex) : rex);
3160 p = doAMode_R( p, i->Ain.SseSF2SI.dst,
3161 vreg2ireg(i->Ain.SseSF2SI.src) );
3166 *p++ = toUChar(i->Ain.SseSDSS.from64 ? 0xF2 : 0xF3);
3168 rexAMode_R( vreg2ireg(i->Ain.SseSDSS.dst),
3169 vreg2ireg(i->Ain.SseSDSS.src) ));
3172 p = doAMode_R( p, vreg2ireg(i->Ain.SseSDSS.dst),
3173 vreg2ireg(i->Ain.SseSDSS.src) );
3177 if (i->Ain.SseLdSt.sz == 8) {
3180 if (i->Ain.SseLdSt.sz == 4) {
3183 if (i->Ain.SseLdSt.sz != 16) {
3187 rexAMode_M( vreg2ireg(i->Ain.SseLdSt.reg), i->Ain.SseLdSt.addr));
3189 *p++ = toUChar(i->Ain.SseLdSt.isLoad ? 0x10 : 0x11);
3190 p = doAMode_M(p, vreg2ireg(i->Ain.SseLdSt.reg), i->Ain.SseLdSt.addr);
3194 vassert(i->Ain.SseLdzLO.sz == 4 || i->Ain.SseLdzLO.sz == 8);
3196 *p++ = toUChar(i->Ain.SseLdzLO.sz==4 ? 0xF3 : 0xF2);
3198 rexAMode_M(vreg2ireg(i->Ain.SseLdzLO.reg),
3199 i->Ain.SseLdzLO.addr));
3202 p = doAMode_M(p, vreg2ireg(i->Ain.SseLdzLO.reg),
3203 i->Ain.SseLdzLO.addr);
3209 rexAMode_R( vreg2ireg(i->Ain.Sse32Fx4.dst),
3210 vreg2ireg(i->Ain.Sse32Fx4.src) ));
3212 switch (i->Ain.Sse32Fx4.op) {
3228 p = doAMode_R(p, vreg2ireg(i->Ain.Sse32Fx4.dst),
3229 vreg2ireg(i->Ain.Sse32Fx4.src) );
3238 rexAMode_R( vreg2ireg(i->Ain.Sse64Fx2.dst),
3239 vreg2ireg(i->Ain.Sse64Fx2.src) ));
3241 switch (i->Ain.Sse64Fx2.op) {
3255 p = doAMode_R(p, vreg2ireg(i->Ain.Sse64Fx2.dst),
3256 vreg2ireg(i->Ain.Sse64Fx2.src) );
3265 rexAMode_R( vreg2ireg(i->Ain.Sse32FLo.dst),
3266 vreg2ireg(i->Ain.Sse32FLo.src) ));
3268 switch (i->Ain.Sse32FLo.op) {
3284 p = doAMode_R(p, vreg2ireg(i->Ain.Sse32FLo.dst),
3285 vreg2ireg(i->Ain.Sse32FLo.src) );
3294 rexAMode_R( vreg2ireg(i->Ain.Sse64FLo.dst),
3295 vreg2ireg(i->Ain.Sse64FLo.src) ));
3297 switch (i->Ain.Sse64FLo.op) {
3311 p = doAMode_R(p, vreg2ireg(i->Ain.Sse64FLo.dst),
3312 vreg2ireg(i->Ain.Sse64FLo.src) );
3321 rexAMode_R( vreg2ireg(i->Ain.SseReRg.dst),
3322 vreg2ireg(i->Ain.SseReRg.src) ));
3324 switch (i->Ain.SseReRg.op) {
3382 p = doAMode_R(p, vreg2ireg(i->Ain.SseReRg.dst),
3383 vreg2ireg(i->Ain.SseReRg.src) );
3389 *p++ = toUChar(0x70 + (i->Ain.SseCMov.cond ^ 1));
3395 rexAMode_R( vreg2ireg(i->Ain.SseCMov.dst),
3396 vreg2ireg(i->Ain.SseCMov.src) ));
3399 p = doAMode_R(p, vreg2ireg(i->Ain.SseCMov.dst),
3400 vreg2ireg(i->Ain.SseCMov.src) );
3409 rexAMode_R( vreg2ireg(i->Ain.SseShuf.dst),
3410 vreg2ireg(i->Ain.SseShuf.src) ));
3413 p = doAMode_R(p, vreg2ireg(i->Ain.SseShuf.dst),
3414 vreg2ireg(i->Ain.SseShuf.src) );
3415 *p++ = (UChar)(i->Ain.SseShuf.order);
3419 //uu UInt vex = vexAMode_M( dvreg2ireg(i->Ain.AvxLdSt.reg),
3420 //uu i->Ain.AvxLdSt.addr );
3422 //uu *p++ = toUChar(i->Ain.AvxLdSt.isLoad ? 0x10 : 0x11);
3423 //uu p = doAMode_M(p, dvreg2ireg(i->Ain.AvxLdSt.reg), i->Ain.AvxLdSt.addr);
3449 rex = clearWBit(rexAMode_M(fake(1), i->Ain.EvCheck.amCounter));
3452 p = doAMode_M(p, fake(1), i->Ain.EvCheck.amCounter);
3462 rex = clearWBit(rexAMode_M(fake(4), i->Ain.EvCheck.amFailAddr));
3465 p = doAMode_M(p, fake(4), i->Ain.EvCheck.amFailAddr);
