Lines Matching refs:NBinary
1046 if (i->ARMin.NBinary.op == ARMneon_VEXT)
1048 if (i->ARMin.NBinary.op == ARMneon_VAND ||
1049 i->ARMin.NBinary.op == ARMneon_VORR ||
1050 i->ARMin.NBinary.op == ARMneon_VXOR)
1052 return showARMNeonDataSize_wrk(i->ARMin.NBinary.size);
1443 i->ARMin.NBinary.op = op;
1444 i->ARMin.NBinary.argL = argL;
1445 i->ARMin.NBinary.argR = argR;
1446 i->ARMin.NBinary.dst = dst;
1447 i->ARMin.NBinary.size = size;
1448 i->ARMin.NBinary.Q = Q;
1929 showARMNeonBinOp(i->ARMin.NBinary.op),
1930 showARMNeonBinOpDataType(i->ARMin.NBinary.op),
1933 ppHRegARM(i->ARMin.NBinary.dst);
1935 ppHRegARM(i->ARMin.NBinary.argL);
1937 ppHRegARM(i->ARMin.NBinary.argR);
2249 addHRegUse(u, HRmWrite, i->ARMin.NBinary.dst);
2252 addHRegUse(u, HRmRead, i->ARMin.NBinary.argL);
2253 addHRegUse(u, HRmRead, i->ARMin.NBinary.argR);
2450 i->ARMin.NBinary.argL = lookupHRegRemap(m, i->ARMin.NBinary.argL);
2451 i->ARMin.NBinary.argR = lookupHRegRemap(m, i->ARMin.NBinary.argR);
2452 i->ARMin.NBinary.dst = lookupHRegRemap(m, i->ARMin.NBinary.dst);
4118 UInt Q = i->ARMin.NBinary.Q ? 1 : 0;
4119 UInt regD = (hregClass(i->ARMin.NBinary.dst) == HRcVec128)
4120 ? (qregNo(i->ARMin.NBinary.dst) << 1)
4121 : dregNo(i->ARMin.NBinary.dst);
4122 UInt regN = (hregClass(i->ARMin.NBinary.argL) == HRcVec128)
4123 ? (qregNo(i->ARMin.NBinary.argL) << 1)
4124 : dregNo(i->ARMin.NBinary.argL);
4125 UInt regM = (hregClass(i->ARMin.NBinary.argR) == HRcVec128)
4126 ? (qregNo(i->ARMin.NBinary.argR) << 1)
4127 : dregNo(i->ARMin.NBinary.argR);
4128 UInt sz1 = i->ARMin.NBinary.size >> 1;
4129 UInt sz2 = i->ARMin.NBinary.size & 1;
4137 switch (i->ARMin.NBinary.op) {
4219 if (i->ARMin.NBinary.size >= 16)
4222 i->ARMin.NBinary.size & 0xf, BITS4(N,Q,M,0),
