Lines Matching refs:__v32qi
34 return (__m256i)__builtin_ia32_pabsb256((__v32qi)__a);
76 return (__m256i)((__v32qi)__a + (__v32qi)__b);
100 return (__m256i)__builtin_ia32_paddsb256((__v32qi)__a, (__v32qi)__b);
112 return (__m256i)__builtin_ia32_paddusb256((__v32qi)__a, (__v32qi)__b);
124 (__m256i)__builtin_ia32_palignr256((__v32qi)__a, (__v32qi)__b, (n)); })
141 return (__m256i)__builtin_ia32_pavgb256((__v32qi)__a, (__v32qi)__b);
153 return (__m256i)__builtin_ia32_pblendvb256((__v32qi)__V1, (__v32qi)__V2,
154 (__v32qi)__M);
165 return (__m256i)((__v32qi)__a == (__v32qi)__b);
189 return (__m256i)((__v32qi)__a > (__v32qi)__b);
249 return (__m256i)__builtin_ia32_pmaddubsw256((__v32qi)__a, (__v32qi)__b);
261 return (__m256i)__builtin_ia32_pmaxsb256((__v32qi)__a, (__v32qi)__b);
279 return (__m256i)__builtin_ia32_pmaxub256((__v32qi)__a, (__v32qi)__b);
297 return (__m256i)__builtin_ia32_pminsb256((__v32qi)__a, (__v32qi)__b);
315 return (__m256i)__builtin_ia32_pminub256((__v32qi)__a, (__v32qi)__b);
333 return __builtin_ia32_pmovmskb256((__v32qi)__a);
459 return __builtin_ia32_psadbw256((__v32qi)__a, (__v32qi)__b);
465 return (__m256i)__builtin_ia32_pshufb256((__v32qi)__a, (__v32qi)__b);
507 return (__m256i)__builtin_ia32_psignb256((__v32qi)__a, (__v32qi)__b);
629 return (__m256i)((__v32qi)__a - (__v32qi)__b);
653 return (__m256i)__builtin_ia32_psubsb256((__v32qi)__a, (__v32qi)__b);
665 return (__m256i)__builtin_ia32_psubusb256((__v32qi)__a, (__v32qi)__b);
677 return (__m256i)__builtin_shufflevector((__v32qi)__a, (__v32qi)__b, 8, 32+8, 9, 32+9, 10, 32+10, 11, 32+11, 12, 32+12, 13, 32+13, 14, 32+14, 15, 32+15, 24, 32+24, 25, 32+25, 26, 32+26, 27, 32+27, 28, 32+28, 29, 32+29, 30, 32+30, 31, 32+31);
701 return (__m256i)__builtin_shufflevector((__v32qi)__a, (__v32qi)__b, 0, 32+0, 1, 32+1, 2, 32+2, 3, 32+3, 4, 32+4, 5, 32+5, 6, 32+6, 7, 32+7, 16, 32+16, 17, 32+17, 18, 32+18, 19, 32+19, 20, 32+20, 21, 32+21, 22, 32+22, 23, 32+23);
