| /external/llvm/include/llvm/Target/ |
| CostTable.h | 44 TypeTy Dst;
52 unsigned len, int ISD, TypeTy Dst, TypeTy Src) {
54 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterDwarf.cpp | 176 const MachineLocation &Dst = Move.getDestination();
180 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
189 assert(Dst.isReg() && "Machine move not supported yet.");
190 OutStreamer.EmitCFIDefCfaRegister(RI->getDwarfRegNum(Dst.getReg(), true));
192 assert(!Dst.isReg() && "Machine move not supported yet.");
194 Dst.getOffset());
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUAsmBackend.cpp | 87 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
89 *Dst = (Value - 4) / 4;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 97 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
131 MachineOperand &Dst = MI->getOperand(0);
133 unsigned DstReg = Dst.getReg();
152 MachineOperand &Dst = MI->getOperand(0);
157 unsigned DstReg = Dst.getReg();
167 MachineOperand &Dst = MI->getOperand(0);
169 unsigned DstReg = Dst.getReg();
185 MachineOperand &Dst = MI->getOperand(0);
192 unsigned DstReg = Dst.getReg();
290 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src)
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| CoreEngine.cpp | 274 ExplodedNodeSet &Dst) {
278 Dst.Add(*I);
452 ExplodedNodeSet Dst;
453 SubEng.processBranch(Cond, Term, Ctx, Pred, Dst,
456 enqueue(Dst);
|
| ExprEngineCXX.cpp | 27 ExplodedNodeSet &Dst) {
28 StmtNodeBuilder Bldr(Pred, Dst, *currBldrCtx);
72 ExplodedNodeSet Dst;
85 evalBind(Dst, CallExpr, Pred, ThisVal, V, true);
88 for (ExplodedNodeSet::iterator I = Dst.begin(), E = Dst.end();
230 ExplodedNodeSet &Dst) {
267 getCheckerManager().runCheckersForPostCall(Dst, DstInvalidated,
272 ExplodedNodeSet &Dst) {
277 StmtNodeBuilder Bldr(Pred, Dst, *currBldrCtx)
[all...] |
| ExprEngineCallAndReturn.cpp | 158 ExplodedNodeSet &Dst) {
164 Dst.Add(Pred);
175 removeDead(Pred, Dst, dyn_cast<ReturnStmt>(LastSt), LCtx,
319 // CEENode -> Dst -> WorkList
332 ExplodedNodeSet Dst;
334 getCheckerManager().runCheckersForPostObjCMessage(Dst, DstPostCall, *Msg,
338 getCheckerManager().runCheckersForPostStmt(Dst, DstPostCall, CE,
341 Dst.insert(DstPostCall);
345 for (ExplodedNodeSet::iterator PSI = Dst.begin(), PSE = Dst.end()
[all...] |
| BugReporter.cpp | 627 const CFGBlock *Dst = BE->getDst();
664 if (const Stmt *S = Dst->getLabel()) {
736 if (*(Src->succ_begin()+1) == Dst)
764 if (*(Src->succ_begin()+1) == Dst) {
784 if (*(Src->succ_begin()+1) == Dst) {
805 if (*(Src->succ_begin()) == Dst) {
833 if (*(Src->succ_begin()+1) == Dst) {
863 if (*(Src->succ_begin()+1) == Dst)
[all...] |
| ExprEngine.cpp | 396 ExplodedNodeSet Dst;
402 Dst.insert(DstI);
406 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
453 ExplodedNodeSet Dst;
454 NodeBuilder Bldr(Tmp, Dst, *currBldrCtx);
461 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
466 ExplodedNodeSet Dst;
469 ProcessAutomaticObjDtor(D.castAs<CFGAutomaticObjDtor>(), Pred, Dst);
472 ProcessBaseDtor(D.castAs<CFGBaseDtor>(), Pred, Dst);
475 ProcessMemberDtor(D.castAs<CFGMemberDtor>(), Pred, Dst);
[all...] |
| /external/llvm/lib/ExecutionEngine/JIT/ |
| JITDwarfEmitter.cpp | 85 const MachineLocation &Dst = Move.getDestination();
98 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
113 if (Dst.isReg()) {
115 JCE->emitULEB128Bytes(RI->getDwarfRegNum(Dst.getReg(), true));
121 int Offset = Dst.getOffset() / stackGrowth;
|
| /external/llvm/lib/Target/R600/ |
| SILowerControlFlow.cpp | 197 unsigned Dst = MI.getOperand(0).getReg();
200 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
205 .addReg(Dst);
216 unsigned Dst = MI.getOperand(0).getReg();
219 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
230 unsigned Dst = MI.getOperand(0).getReg();
234 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
245 unsigned Dst = MI.getOperand(0).getReg();
249 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
377 unsigned Dst = MI.getOperand(0).getReg()
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| DependenceAnalysis.h | 68 Src(Source), Dst(Destination) {}
99 Instruction *getDst() const { return Dst; }
171 Instruction *Src, *Dst;
187 Instruction *Dst,
250 /// depends - Tests for a dependence between the Src and Dst instructions.
254 /// if it appears that control flow can reach from Src to Dst
257 Instruction *Dst,
313 const SCEV *Dst;
425 /// establishNestingLevels - Examines the loop nesting of the Src and Dst
442 /// ... - loops containing Src but not Dst
[all...] |
| /external/llvm/lib/CodeGen/ |
| TailDuplication.cpp | 282 unsigned Dst = Copy->getOperand(0).getReg();
285 MRI->constrainRegClass(Src, MRI->getRegClass(Dst))) {
287 MRI->replaceRegWith(Dst, Src);
[all...] |
| RegisterCoalescer.cpp | 132 /// which are the src/dst of the copy instruction CopyMI. This returns
216 unsigned &Src, unsigned &Dst,
219 Dst = MI->getOperand(0).getReg();
224 Dst = MI->getOperand(0).getReg();
257 unsigned Src, Dst, SrcSub, DstSub;
258 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
262 // If one register is a physreg, it must be Dst.
264 if (TargetRegisterInfo::isPhysicalRegister(Dst))
266 std::swap(Src, Dst);
273 if (TargetRegisterInfo::isPhysicalRegister(Dst)) {
[all...] |
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 838 /// StoreIntToMemory - Fills the StoreBytes bytes of memory starting from Dst
840 static void StoreIntToMemory(const APInt &IntVal, uint8_t *Dst,
848 memcpy(Dst, Src, StoreBytes);
856 memcpy(Dst + StoreBytes, Src, sizeof(uint64_t));
860 memcpy(Dst, Src + sizeof(uint64_t) - StoreBytes, StoreBytes);
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 103 const MCOperand &Dst = MI->getOperand(0);
113 printRegName(O, Dst.getReg());
126 const MCOperand &Dst = MI->getOperand(0);
135 printRegName(O, Dst.getReg());
[all...] |
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGCall.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CStringChecker.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| DependenceAnalysis.cpp | 190 return Src->mayReadFromMemory() && Dst->mayReadFromMemory();
196 return Src->mayWriteToMemory() && Dst->mayWriteToMemory();
202 return Src->mayWriteToMemory() && Dst->mayReadFromMemory();
208 return Src->mayReadFromMemory() && Dst->mayWriteToMemory();
660 // Examines the loop nesting of the Src and Dst
677 // ... - loops containing Src but not Dst
678 // SrcLevels - innermost loop containing Src but not Dst
679 // ... - loops containing Dst but not Src
680 // MaxLevels - innermost loops containing Dst but not Src
699 // to A (the Src) and the load from A (the Dst), we'll note that the
[all...] |
| /external/llvm/lib/Transforms/Instrumentation/ |
| AddressSanitizer.cpp | 576 Value *Dst = MI->getDest();
594 instrumentMemIntrinsicParam(MI, Dst, Length, InsertBefore, true);
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| ScalarReplAggregates.cpp | 730 // Noop transfer. Src == Dst
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 730 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
732 assert(Dst && Src && "Bad sub-register");
735 DstRegs.insert(Dst);
737 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 729 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
730 // => ext $dst, $src, size, pos
769 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
771 // => ins $dst, $src, size, pos, $src1
[all...] |
