| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 32 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| SparcISelLowering.cpp | 476 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
484 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
491 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
507 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
705 // Custom legalize GlobalAddress nodes into LO/HI parts.
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsJITInfo.cpp | 172 // addiu $t9, $t9, %lo(NewVal)
179 int Lo = (int)(NewVal & 0xffff);
182 *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo;
219 int Lo = (int)(EmittedAddr & 0xffff);
222 // addiu t9, t9, %lo(EmittedAddr)
227 JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
232 JCE.emitWordBE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
|
| Mips16ISelDAGToDAG.cpp | 42 SDNode *Lo = 0, *Hi = 0;
49 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
50 InFlag = SDValue(Lo, 1);
56 return std::make_pair(Lo, Hi);
200 // addiu $2, $2, %lo($CPI1_0)
204 // lwc1 $f0, %lo($CPI1_0)($2)
205 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
|
| MipsLongBranch.cpp | 263 int64_t Lo = SignExtend64<16>(Offset & 0xffff);
273 // addiu $at, $at, %lo($tgt - $baltgt)
295 .addReg(Mips::AT).addImm(Lo);
316 // daddiu $at, $at, %lo($tgt - $baltgt)
351 .addReg(Mips::AT_64).addImm(Lo);
|
| MipsSEISelDAGToDAG.cpp | 105 // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
120 // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
134 // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
150 // 1. addiu $2, $2, %lo(_gp_disp)
184 SDNode *Lo = 0, *Hi = 0;
191 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
192 InFlag = SDValue(Lo, 1);
198 return std::make_pair(Lo, Hi);
269 // addiu $2, $2, %lo($CPI1_0)
273 // lwc1 $f0, %lo($CPI1_0)($2
[all...] |
| MipsISelLowering.h | 44 // No relation with Mips Lo register
45 Lo,
|
| MipsISelLowering.cpp | 102 SDValue Lo = getTargetNode(Op, DAG, MipsII::MO_ABS_LO);
105 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
119 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
120 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
151 case MipsISD::Lo: return "MipsISD::Lo";
415 // multHi/Lo: product of multiplication
416 // Lo0: initial value of Lo registe
[all...] |
| /external/llvm/include/llvm/Support/ |
| GCOV.h | 138 uint64_t Lo = readInt();
140 uint64_t Result = Lo | (Hi << 32);
|
| MathExtras.h | 227 // leading zeros in hi portion plus all bits in lo portion
230 // get lo portion
231 uint32_t Lo = Lo_32(Value);
233 Count = CountLeadingZeros_32(Lo)+32;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.h | 43 Hi, Lo, // Hi/Lo operations, typically on a global address.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 14 // computation in two identical registers of a smaller type. The Lo/Hi part
30 // These routines assume that the Lo/Hi part is stored first in memory on
31 // little/big-endian machines, followed by the Hi/Lo part. This means that
32 // they cannot be used as is on vectors, for which Lo is always stored first.
34 SDValue &Lo, SDValue &Hi) {
36 GetExpandedOp(Op, Lo, Hi);
39 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) {
53 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi);
54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
[all...] |
| LegalizeDAG.cpp | 399 SDValue Lo = Val;
404 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
410 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
531 SDValue Lo, Hi;
533 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
548 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
558 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
560 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
679 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
681 if (TLI.isBigEndian()) std::swap(Lo, Hi)
[all...] |
| LegalizeVectorOps.cpp | 450 SDValue Lo, Hi, ShAmt;
454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
455 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
471 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
476 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
479 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT)
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 237 SDValue Lo, Hi;
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
243 std::swap(Lo, Hi);
248 JoinIntegers(Lo, Hi));
[all...] |
| LegalizeVectorTypes.cpp | 479 SDValue Lo, Hi;
495 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
497 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
498 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
499 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
500 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
501 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
502 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
503 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
504 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break
[all...] |
| SelectionDAGBuilder.cpp | 124 SDValue Lo, Hi;
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
139 std::swap(Lo, Hi);
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
151 Lo = Val;
153 std::swap(Lo, Hi);
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
2441 uint64_t lo = (lowValue - lowBound).getZExtValue(); local
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
60 Hi, Lo,
|
| PPCISelDAGToDAG.cpp | 126 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
139 if (isa<ConstantSDNode>(N) || N.getOpcode() == PPCISD::Lo ||
[all...] |
| /external/skia/legacy/src/core/ |
| SkMath.cpp | 102 uint32_t lo = C + (B << 16); local
103 int32_t hi = A + (B >> 16) + (lo < C);
106 hi = -hi - Sk32ToBool(lo);
107 lo = 0 - lo;
112 SkASSERT(((int32_t)lo >> 31) == hi);
114 return lo;
122 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
123 int roundBit = (lo >> (shift - 1)) & 1;
124 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit
[all...] |
| /external/skia/src/core/ |
| SkMath.cpp | 101 uint32_t lo = C + (B << 16); local
102 int32_t hi = A + (B >> 16) + (lo < C);
105 hi = -hi - Sk32ToBool(lo);
106 lo = 0 - lo;
111 SkASSERT(((int32_t)lo >> 31) == hi);
113 return lo;
121 // we want (hi << (32 - shift)) | (lo >> shift) but rounded
122 int roundBit = (lo >> (shift - 1)) & 1;
123 return ((hi << (32 - shift)) | (lo >> shift)) + roundBit
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 574 SDValue Lo(Hi.getNode(), 1);
575 SDValue Ops[] = { Lo, Hi };
591 SDValue Lo(Hi.getNode(), 1);
592 SDValue Ops[] = { Lo, Hi };
688 SDValue Lo(Hi.getNode(), 1);
689 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
696 SDValue Lo(Hi.getNode(), 1);
697 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
707 SDValue Lo(Hi.getNode(), 1);
712 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi)
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_mips_isel.c | 349 // store hi,lo as Ity_I32's
1345 HReg hi, lo; local
[all...] |
| /external/clang/lib/Sema/ |
| SemaStmt.cpp | 738 Expr *Lo = CS->getLHS();
740 if (Lo->isTypeDependent() || Lo->isValueDependent()) {
751 CheckConvertedConstantExpression(Lo, CondType, LoVal, CCEK_CaseValue);
756 Lo = ConvLo.take();
760 LoVal = Lo->EvaluateKnownConstInt(Context);
764 Lo = DefaultLvalueConversion(Lo).take();
765 Lo = ImpCastExprToType(Lo, CondType, CK_IntegralCast).take()
[all...] |
