| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| /external/libffi/src/mips/ |
| ffitarget.h | 128 # define SRL srl
135 # define SRL dsrl
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 91 SRL, SRA, SHL,
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 318 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/llvm/include/llvm/TableGen/ |
| Record.h | 930 enum BinaryOp { ADD, SHL, SRA, SRL, STRCONCAT, CONCAT, EQ };
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 729 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
738 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 498 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
