| /external/llvm/lib/CodeGen/ |
| CallingConvLower.cpp | 72 MVT ArgVT = Ins[i].VT;
90 MVT VT = Outs[i].VT;
92 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
104 MVT VT = Outs[i].VT;
106 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
109 << EVT(VT).getEVTString() << '\n'
[all...] |
| TargetLoweringBase.cpp | 631 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
635 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
636 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
640 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
641 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
759 /// VT must be a legal type.
760 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
761 assert(isTypeLegal(VT));
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.cpp | 81 EVT ArgVT = Ins[i].VT;
117 EVT VT = Outs[i].VT;
119 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this, -1, -1, false)){
121 << VT.getEVTString() << "\n";
147 EVT ArgVT = Outs[i].VT;
185 EVT VT = Ins[i].VT;
187 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this, -1, -1, false))
[all...] |
| /external/llvm/utils/TableGen/ |
| CallingConvEmitter.cpp | 88 Record *VT = VTs->getElementAsRecord(i);
90 O << "LocVT == " << getEnumName(getValueType(VT));
|
| DAGISelMatcher.cpp | 210 OS.indent(indent) << "EmitInteger " << Val << " VT=" << VT << '\n';
215 OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << VT << '\n';
224 OS << " VT=" << VT << '\n';
293 return HashString(Val) ^ VT;
|
| CodeGenTarget.cpp | 468 MVT::SimpleValueType VT;
473 VT = OverloadedVTs[MatchTy];
479 VT == MVT::iAny || VT == MVT::vAny) &&
482 VT = getValueType(TyEl->getValueAsDef("VT"));
484 if (EVT(VT).isOverloaded()) {
485 OverloadedVTs.push_back(VT);
490 if (VT == MVT::isVoid)
493 IS.RetVTs.push_back(VT);
[all...] |
| IntrinsicEmitter.cpp | 249 static void EncodeFixedValueType(MVT::SimpleValueType VT,
251 if (EVT(VT).isInteger()) {
252 unsigned BitWidth = EVT(VT).getSizeInBits();
263 switch (VT) {
294 MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT"));
297 switch (VT) {
331 if (EVT(VT).isVector()) {
332 EVT VVT = VT;
346 EncodeFixedValueType(VT, Sig)
[all...] |
| /external/clang/include/clang/AST/ |
| DeclContextInternals.h | 171 DeclsTy *VT = new DeclsTy();
172 VT->push_back(OldD);
173 Data = VT;
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 29 EVT VT;
30 VT.LLVMTy = IntegerType::get(Context, BitWidth);
31 assert(VT.isExtended() && "Type is not extended!");
32 return VT;
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT,
38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements);
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 52 EVT VT = MVT::i32;
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
98 VT = MVT::i16;
101 VT = MVT::i8;
105 Loads[i] = DAG.getLoad(VT, dl, Chain,
121 VT = MVT::i16;
124 VT = MVT::i8;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 102 MVT VT = Node->getSimpleValueType(ResNo);
105 if (TLI->isTypeLegal(VT))
106 UseRC = TLI->getRegClassFor(VT);
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
166 DstRC = TLI->getRegClassFor(VT);
425 MVT VT, DebugLoc DL)
[all...] |
| SelectionDAGPrinter.cpp | 93 EVT VT = Op.getValueType();
94 if (VT == MVT::Glue)
96 else if (VT == MVT::Other)
|
| FunctionLoweringInfo.cpp | 172 EVT VT = ValueVTs[vti];
173 unsigned NumRegisters = TLI.getNumRegisters(Fn->getContext(), VT);
210 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
211 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
272 "PHIs with non-vector integer types should have a single VT.");
|
| ResourcePriorityQueue.cpp | 97 MVT VT = ScegN->getSimpleValueType(i);
98 if (TLI->isTypeLegal(VT)
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
136 if (TLI->isTypeLegal(VT)
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) {
335 MVT VT = SU->getNode()->getSimpleValueType(i);
336 if (TLI->isTypeLegal(VT)
337 && TLI->getRegClassFor(VT)
338 && TLI->getRegClassFor(VT)->getID() == RCId
[all...] |
| LegalizeTypesGeneric.cpp | 418 EVT VT = N->getValueType(0);
419 assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
421 unsigned NumElts = VT.getVectorNumElements();
427 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 211 EVT VT = Node->getValueType(0);
212 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
215 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI, imm);
216 return CurDAG->getMachineNode(Opc, dl, VT, TFI, imm);
|
| /external/clang/lib/CodeGen/ |
| CodeGenTypes.cpp | 459 const VectorType *VT = cast<VectorType>(Ty);
460 ResultType = llvm::VectorType::get(ConvertType(VT->getElementType()),
461 VT->getNumElements());
|
| /external/guava/guava/src/com/google/common/base/ |
| Ascii.java | 167 public static final byte VT = 11;
|
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 113 MVT VT;
124 InputArg() : VT(MVT::Other), Used(false) {}
125 InputArg(ArgFlagsTy flags, EVT vt, bool used,
128 VT = vt.getSimpleVT();
138 MVT VT;
152 OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed,
156 VT = vt.getSimpleVT();
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 267 EVT VT = LHS.getValueType();
270 SDNode *Carry = CurDAG->getMachineNode(Sltu_op, DL, VT, Ops, 2);
272 SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, DL, VT,
275 SDNode *Result = CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
|
| MipsSEISelDAGToDAG.cpp | 212 EVT VT = LHS.getValueType();
214 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops, 2);
215 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
217 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 116 EVT VT = Op.getValueType();
123 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
127 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
129 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
132 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
135 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
138 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
141 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
144 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
147 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1))
[all...] |
| AMDILISelLowering.cpp | 96 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
100 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
101 setOperationAction(ISD::SUBE, VT, Expand);
102 setOperationAction(ISD::SUBC, VT, Expand);
103 setOperationAction(ISD::ADDE, VT, Expand);
104 setOperationAction(ISD::ADDC, VT, Expand);
105 setOperationAction(ISD::BRCOND, VT, Custom);
106 setOperationAction(ISD::BR_JT, VT, Expand);
107 setOperationAction(ISD::BRIND, VT, Expand);
109 setOperationAction(ISD::SREM, VT, Expand)
[all...] |
| SIISelLowering.cpp | 118 if (Arg.VT.isVector()) {
121 NewArg.VT = Arg.VT.getVectorElementType();
131 NewArg.PartOffset += NewArg.VT.getStoreSize();
163 MVT VT = VA.getLocVT();
165 if (VT == MVT::i64) {
170 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
174 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
177 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
180 if (Arg.VT.isVector())
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 245 MVT::SimpleValueType VT = (strcmp(Modifier+6,"64") == 0) ?
248 Reg = getX86SubSuperRegister(Reg, VT);
|
