1 tblgen - Target Description To C++ Code Generator 2 ================================================= 3 4 SYNOPSIS 5 -------- 6 7 :program:`tblgen` [*options*] [*filename*] 8 9 DESCRIPTION 10 ----------- 11 12 :program:`tblgen` translates from target description (``.td``) files into C++ 13 code that can be included in the definition of an LLVM target library. Most 14 users of LLVM will not need to use this program. It is only for assisting with 15 writing an LLVM target backend. 16 17 The input and output of :program:`tblgen` is beyond the scope of this short 18 introduction. Please see :doc:`../TableGenFundamentals`. 19 20 The *filename* argument specifies the name of a Target Description (``.td``) 21 file to read as input. 22 23 OPTIONS 24 ------- 25 26 .. option:: -help 27 28 Print a summary of command line options. 29 30 .. option:: -o filename 31 32 Specify the output file name. If ``filename`` is ``-``, then 33 :program:`tblgen` sends its output to standard output. 34 35 .. option:: -I directory 36 37 Specify where to find other target description files for inclusion. The 38 ``directory`` value should be a full or partial path to a directory that 39 contains target description files. 40 41 .. option:: -asmparsernum N 42 43 Make -gen-asm-parser emit assembly writer number ``N``. 44 45 .. option:: -asmwriternum N 46 47 Make -gen-asm-writer emit assembly writer number ``N``. 48 49 .. option:: -class className 50 51 Print the enumeration list for this class. 52 53 .. option:: -print-records 54 55 Print all records to standard output (default). 56 57 .. option:: -print-enums 58 59 Print enumeration values for a class 60 61 .. option:: -print-sets 62 63 Print expanded sets for testing DAG exprs. 64 65 .. option:: -gen-emitter 66 67 Generate machine code emitter. 68 69 .. option:: -gen-register-info 70 71 Generate registers and register classes info. 72 73 .. option:: -gen-instr-info 74 75 Generate instruction descriptions. 76 77 .. option:: -gen-asm-writer 78 79 Generate the assembly writer. 80 81 .. option:: -gen-disassembler 82 83 Generate disassembler. 84 85 .. option:: -gen-pseudo-lowering 86 87 Generate pseudo instruction lowering. 88 89 .. option:: -gen-dag-isel 90 91 Generate a DAG (Directed Acycle Graph) instruction selector. 92 93 .. option:: -gen-asm-matcher 94 95 Generate assembly instruction matcher. 96 97 .. option:: -gen-dfa-packetizer 98 99 Generate DFA Packetizer for VLIW targets. 100 101 .. option:: -gen-fast-isel 102 103 Generate a "fast" instruction selector. 104 105 .. option:: -gen-subtarget 106 107 Generate subtarget enumerations. 108 109 .. option:: -gen-intrinsic 110 111 Generate intrinsic information. 112 113 .. option:: -gen-tgt-intrinsic 114 115 Generate target intrinsic information. 116 117 .. option:: -gen-enhanced-disassembly-info 118 119 Generate enhanced disassembly info. 120 121 .. option:: -version 122 123 Show the version number of this program. 124 125 EXIT STATUS 126 ----------- 127 128 If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error 129 occurs, it will exit with a non-zero value. 130
