| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/asn1/ |
| ASN1Encoding.java | 6 static final String DL = "DL";
|
| /external/llvm/include/llvm/Support/ |
| DebugLoc.h | 32 DebugLoc DL;
33 DL.LineCol = 1;
34 return DL;
40 DebugLoc DL;
41 DL.LineCol = 2;
42 return DL;
95 bool operator==(const DebugLoc &DL) const {
96 return LineCol == DL.LineCol && ScopeIdx == DL.ScopeIdx;
98 bool operator!=(const DebugLoc &DL) const { return !(*this == DL);
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 84 DebugLoc DL, SelectionDAG &DAG) const {
85 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
115 DebugLoc DL = Op.getDebugLoc();
123 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
127 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
129 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
132 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
135 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
138 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
141 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1)
[all...] |
| SILowerControlFlow.cpp | 138 DebugLoc DL = From.getDebugLoc();
139 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
147 DebugLoc DL = MI.getDebugLoc();
156 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
161 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
173 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
178 DebugLoc DL = MI.getDebugLoc();
182 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
196 DebugLoc DL = MI.getDebugLoc()
[all...] |
| AMDILISelLowering.cpp | 334 DebugLoc DL = Op.getDebugLoc();
344 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data);
350 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift);
352 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
356 Data = DAG.getSExtOrTrunc(Data, DL, Op.getOperand(0).getValueType());
398 DebugLoc DL = Op.getDebugLoc();
416 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
419 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
422 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
425 jq = DAG.getSExtOrTrunc(jq, DL, INTTY)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 42 MachineBasicBlock::iterator I, DebugLoc DL,
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
63 DebugLoc DL;
64 if (I != MBB.end()) DL = I->getDebugLoc();
73 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
91 DebugLoc DL;
92 if (I != MBB.end()) DL = I->getDebugLoc();
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
| A15SDOptimizer.cpp | 72 DebugLoc DL,
78 DebugLoc DL,
84 DebugLoc DL,
89 DebugLoc DL,
94 DebugLoc DL, unsigned DReg, unsigned Lane,
99 DebugLoc DL);
433 DebugLoc DL,
439 DL,
452 DebugLoc DL,
458 DL,
[all...] |
| ARMTargetMachine.h | 71 const DataLayout DL; // Calculates type size & alignment
97 virtual const DataLayout *getDataLayout() const { return &DL; }
108 const DataLayout DL; // Calculates type size & alignment
141 virtual const DataLayout *getDataLayout() const { return &DL; }
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 49 DebugLoc DL;
54 SDDbgValue(MDNode *mdP, SDNode *N, unsigned R, uint64_t off, DebugLoc dl,
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
63 SDDbgValue(MDNode *mdP, const Value *C, uint64_t off, DebugLoc dl,
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
71 SDDbgValue(MDNode *mdP, unsigned FI, uint64_t off, DebugLoc dl, unsigned O) :
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 69 MachineBasicBlock::iterator I, DebugLoc DL,
91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
105 DebugLoc DL;
106 if (I != MBB.end()) DL = I->getDebugLoc();
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
121 DebugLoc DL;
122 if (I != MBB.end()) DL = I->getDebugLoc();
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
177 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
180 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize)
[all...] |
| MipsISelLowering.cpp | 99 DebugLoc DL = Op.getDebugLoc();
103 return DAG.getNode(ISD::ADD, DL, Ty,
104 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
105 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
110 DebugLoc DL = Op.getDebugLoc();
113 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
115 SDValue Load = DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
119 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, getTargetNode(Op, DAG, LoFlag));
120 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
125 DebugLoc DL = Op.getDebugLoc()
[all...] |
| MipsSEISelDAGToDAG.cpp | 87 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
107 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
109 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
111 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
121 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
123 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
136 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
138 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
139 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
165 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg
[all...] |
| MipsLongBranch.cpp | 83 void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
219 DebugLoc DL, MachineBasicBlock *MBBOpnd) {
223 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
245 DebugLoc DL = I.Br->getDebugLoc();
283 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
285 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
289 .append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
290 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
294 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
296 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT
[all...] |
| Mips16ISelDAGToDAG.cpp | 40 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty,
43 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
49 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
54 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
69 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
78 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
80 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
82 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
83 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
99 DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc()
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 49 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
86 DL = MBBI->getDebugLoc();
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
115 DebugLoc DL = MBBI->getDebugLoc();
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
148 DL = MBBI->getDebugLoc();
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
[all...] |
| MSP430TargetMachine.h | 34 const DataLayout DL; // Calculates type size & alignment
50 virtual const DataLayout *getDataLayout() const { return &DL;}
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 278 DebugLoc DL)const{
287 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
291 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
300 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
302 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
335 MachineBasicBlock::iterator I, DebugLoc DL,
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
354 BuildMI(MBB, I, DL, get(XCore::SETSP_1r))
368 DebugLoc DL;
[all...] |
| XCoreTargetMachine.h | 29 const DataLayout DL; // Calculates type size & alignment
56 virtual const DataLayout *getDataLayout() const { return &DL; }
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 37 MachineBasicBlock::iterator I, DebugLoc DL,
42 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg)
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV8rr), DestReg)
50 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg)
54 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg)
58 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg)
62 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg)
66 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg)
265 DebugLoc DL) const {
274 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB)
[all...] |
| NVPTXInstrInfo.h | 54 MachineBasicBlock::iterator I, DebugLoc DL,
74 DebugLoc DL) const;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetMachine.h | 30 const DataLayout DL;
59 const DataLayout *getDataLayout() const { return &DL; }
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonTargetMachine.h | 30 const DataLayout DL; // Calculates type size & alignment.
71 virtual const DataLayout *getDataLayout() const { return &DL; }
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeTargetMachine.h | 33 const DataLayout DL; // Calculates type size & alignment
61 { return &DL;}
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 224 DebugLoc DL,
226 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
233 DebugLoc DL,
236 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
246 DebugLoc DL,
250 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
257 DebugLoc DL,
261 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
268 DebugLoc DL,
273 return BuildMI(BB, MII, DL, MCID, DestReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetMachine.h | 81 const DataLayout DL; // Calculates type size & alignment
91 virtual const DataLayout *getDataLayout() const { return &DL; }
110 const DataLayout DL; // Calculates type size & alignment
120 virtual const DataLayout *getDataLayout() const { return &DL; }
|
