| /external/llvm/lib/Target/XCore/ |
| XCoreSubtarget.cpp | 27 const std::string &CPU, const std::string &FS)
28 : XCoreGenSubtargetInfo(TT, CPU, FS)
|
| XCoreSubtarget.h | 35 const std::string &FS);
39 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| XCoreTargetMachine.cpp | 24 StringRef CPU, StringRef FS,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS),
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430Subtarget.cpp | 28 const std::string &FS) :
29 MSP430GenSubtargetInfo(TT, CPU, FS) {
33 ParseSubtargetFeatures(CPUName, FS);
|
| MSP430Subtarget.h | 34 const std::string &FS);
38 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| MSP430TargetMachine.cpp | 30 StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS),
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64Subtarget.cpp | 28 AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS)
29 : AArch64GenSubtargetInfo(TT, CPU, FS)
34 ParseSubtargetFeatures(CPU, FS);
|
| AArch64Subtarget.h | 40 AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS);
44 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcSubtarget.cpp | 27 const std::string &FS, bool is64Bit) :
28 SparcGenSubtargetInfo(TT, CPU, FS),
45 ParseSubtargetFeatures(CPUName, FS);
|
| SparcTargetMachine.cpp | 29 StringRef CPU, StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS, is64bit),
80 StringRef FS,
85 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
92 StringRef FS,
97 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| SparcSubtarget.h | 35 const std::string &FS, bool is64bit);
43 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXSubtarget.cpp | 36 const std::string &FS, bool is64Bit)
37 : NVPTXGenSubtargetInfo(TT, CPU, FS),
47 ParseSubtargetFeatures((CPU.empty() ? defCPU : CPU), FS);
49 // Get the TargetName from the FS if available
50 if (FS.empty() && CPU.empty())
|
| NVPTXTargetMachine.cpp | 65 StringRef FS,
71 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
72 Subtarget(TT, CPU, FS, is64bit),
83 StringRef CPU, StringRef FS,
87 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
93 StringRef CPU, StringRef FS,
97 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| /external/clang/lib/Analysis/ |
| FormatStringParsing.h | 47 bool ParseLengthModifier(FormatSpecifier &FS, const char *&Beg, const char *E,
51 T FS;
58 const T &fs)
59 : FS(fs), Start(start), Stop(false) {}
66 return FS;
68 const T &getValue() { return FS; }
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSubtarget.cpp | 41 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
42 HexagonGenSubtargetInfo(TT, CPU, FS),
62 ParseSubtargetFeatures(CPUString, FS);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeSubtarget.cpp | 28 const std::string &FS):
29 MBlazeGenSubtargetInfo(TT, CPU, FS),
37 ParseSubtargetFeatures(CPUName, FS);
|
| /external/llvm/lib/Target/CppBackend/ |
| CPPTargetMachine.h | 26 StringRef CPU, StringRef FS, const TargetOptions &Options,
29 : TargetMachine(T, TT, CPU, FS, Options) {}
|
| /ndk/build/awk/ |
| extract-pid.awk | 27 FS=" "
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/sys/ |
| reg.h | 53 # define FS 25
69 # define FS 9
|
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
| reg.h | 53 # define FS 25
69 # define FS 9
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/sys/ |
| reg.h | 53 # define FS 25
69 # define FS 9
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetMachine.cpp | 40 StringRef CPU, StringRef FS, const TargetOptions &Options,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, isLittle, RM),
64 StringRef CPU, StringRef FS, const TargetOptions &Options,
67 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
73 StringRef CPU, StringRef FS, const TargetOptions &Options,
76 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetMachine.cpp | 36 StringRef CPU, StringRef FS,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42 Subtarget(TT, CPU, FS, is64Bit),
56 StringRef CPU, StringRef FS,
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
66 StringRef CPU, StringRef FS,
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMSubtarget.cpp | 45 const std::string &FS)
46 : ARMGenSubtargetInfo(TT, CPU, FS)
53 resetSubtargetFeatures(CPU, FS);
105 std::string FS =
107 if (!FS.empty()) {
109 resetSubtargetFeatures(CPU, FS);
113 void ARMSubtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
122 if (!FS.empty()) {
124 ArchFS = ArchFS + "," + FS.str();
126 ArchFS = FS;
[all...] |
| /frameworks/compile/slang/ |
| slang_rs_ast_replace.cpp | 115 void RSASTReplace::VisitForStmt(clang::ForStmt *FS) {
116 if (matchesStmt(FS->getInit())) {
117 FS->setInit(mNewStmt);
118 } else if (matchesExpr(FS->getCond())) {
119 FS->setCond(mNewExpr);
120 } else if (matchesExpr(FS->getInc())) {
121 FS->setInc(mNewExpr);
122 } else if (matchesStmt(FS->getBody())) {
123 FS->setBody(mNewStmt);
125 VisitStmt(FS);
[all...] |
