| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
38 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
40 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
42 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
44 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
62 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
67 void DecodeVPERMMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
|
| X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
31 unsigned ZMask = Imm & 15;
32 unsigned CountD = (Imm >> 4) & 3;
33 unsigned CountS = (Imm >> 6) & 3;
64 void DecodePALIGNRMask(MVT VT, unsigned Imm,
67 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8);
85 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) {
91 unsigned NewImm = Imm;
97 if (NumLaneElts == 4) NewImm = Imm; // reload imm
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 106 // reg [asr|lsl|lsr|ror|rrx] imm
109 // reg, the second is the shift amount (or reg0 if not present or imm). The
110 // third operand encodes the shift opcode and the imm if a reg isn't present.
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
113 return ShOp | (Imm << 3);
122 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
123 /// the 8-bit imm value.
124 static inline unsigned getSOImmValImm(unsigned Imm) {
125 return Imm & 0xFF
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize,
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs);
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL));
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize,
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs);
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL));
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize,
43 unsigned Shamt = CountTrailingZeros_64(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize
[all...] |
| MipsAnalyzeImmediate.h | 25 /// Analyze - Get an instrucion sequence to load immediate Imm. The last
28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
36 /// load immediate Imm
37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
40 /// load immediate Imm
41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
44 /// load immediate Imm
45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
47 /// GetInstSeqLs - Get instrucion sequences to load immediate Imm.
48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs)
[all...] |
| Mips16InstrInfo.h | 85 int64_t Imm, MachineBasicBlock &MBB,
94 // build the proper one based on the Imm field
97 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
100 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const;
|
| MipsISelDAGToDAG.h | 56 /// (reg + imm).
76 inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
77 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
|
| MipsSEInstrInfo.h | 75 unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 88 IntFloatUnion Imm;
90 Imm.I = MO.getImm();
92 Imm.F = MO.getFPImm();
96 if (Imm.I >= 0 && Imm.I <= 64)
97 return 128 + Imm.I;
99 if (Imm.I >= -16 && Imm.I <= -1)
100 return 192 + abs(Imm.I);
102 if (Imm.F == 0.5f
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
20 return Addr+Size+Imm;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 74 inline SDValue getI32Imm(unsigned Imm) {
75 return CurDAG->getTargetConstant(Imm, MVT::i32);
80 inline SDValue getI64Imm(uint64_t Imm) {
81 return CurDAG->getTargetConstant(Imm, MVT::i64);
85 inline SDValue getSmallIPtrImm(unsigned Imm) {
86 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
116 /// a base register plus a signed 16-bit displacement [r+imm].
149 /// be represented by [r+imm], which are preferred.
161 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
287 static bool isIntS16Immediate(SDNode *N, short &Imm) {
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 89 inline SDValue getI32Imm(unsigned Imm) {
90 return CurDAG->getTargetConstant(Imm, MVT::i32);
100 static bool isIntS32Immediate(SDNode *N, int32_t &Imm) {
105 Imm = (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
107 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
109 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
113 return isIntS32Immediate(Op.getNode(), Imm);
119 /// can be more efficiently represented with [r+imm].
127 int32_t imm = 0
154 int32_t imm = 0; local
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32); local
[all...] |
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 237 unsigned Imm;
239 Imm = 0;
241 Imm = 1;
243 Imm = 2;
245 Imm = 3;
247 Imm = 4;
249 Imm = 5;
251 Imm = 6;
253 Imm = 7;
259 CI->getArgOperand(1), Builder.getInt8(Imm));
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 208 uint64_t Imm);
229 uint64_t Imm);
238 uint64_t Imm, MVT ImmType);
246 uint64_t Imm);
292 uint64_t Imm);
317 uint64_t Imm);
332 uint64_t Imm);
|
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfo.h | 211 virtual bool isLegalAddImmediate(int64_t Imm) const;
217 virtual bool isLegalICmpImmediate(int64_t Imm) const;
251 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
|
| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 49 unsigned Imm = MI->getOperand(OpNum).getImm();
51 if (Imm == 2) {
53 } else if (Imm == 1) {
55 } else if (Imm == 0) {
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86IntelInstPrinter.cpp | 54 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
55 switch (Imm) {
78 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
79 switch (Imm) {
|
| X86ATTInstPrinter.cpp | 64 int64_t Imm = MI->getOperand(Op).getImm() & 0xf;
65 switch (Imm) {
88 int64_t Imm = MI->getOperand(Op).getImm() & 0x1f;
89 switch (Imm) {
159 O << markup("<imm:")
164 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
168 O << markup("<imm:")
209 << markup("<imm:")
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.h | 81 inline SDValue getI32Imm(unsigned Imm) {
82 return CurDAG->getTargetConstant(Imm, MVT::i32);
|
| /external/llvm/lib/Analysis/ |
| TargetTransformInfo.cpp | 95 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
96 return PrevTTI->isLegalAddImmediate(Imm);
99 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
100 return PrevTTI->isLegalICmpImmediate(Imm);
136 unsigned TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
137 return PrevTTI->getIntImmCost(Imm, Ty);
443 bool isLegalAddImmediate(int64_t Imm) const {
447 bool isLegalICmpImmediate(int64_t Imm) const {
482 unsigned getIntImmCost(const APInt &Imm, Type *Ty) const {
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.h | 64 int64_t Imm) const;
166 uint64_t Imm) const;
179 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
|
| SIISelLowering.cpp | 438 } Imm;
441 Imm.I = Node->getSExtValue();
443 Imm.F = Node->getValueAPF().convertToFloat();
447 if ((Imm.I >= -16 && Imm.I <= 64) ||
448 Imm.F == 0.5f || Imm.F == -0.5f ||
449 Imm.F == 1.0f || Imm.F == -1.0f ||
450 Imm.F == 2.0f || Imm.F == -2.0f |
[all...] |
| SIInstrInfo.h | 42 int64_t Imm) const;
|
| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 27 enum MapKind { Operand, Imm, Reg };
31 uint64_t Imm; // Integer immedate value.
104 OperandMap[BaseIdx + i].Kind = OpData::Imm;
105 OperandMap[BaseIdx + i].Data.Imm = II->getValue();
235 case OpData::Imm:
237 << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 662 bool A64Imms::isLogicalImm(unsigned RegWidth, uint64_t Imm, uint32_t &Bits) {
669 if (Imm == 0) return false;
673 uint64_t ReplicatedMask = Imm & RepeatMask;
681 if (((Imm >> i) & RepeatMask) != ReplicatedMask) {
691 Rotation = CountTrailingZeros_64(Imm);
695 Rotation = RegWidth == 64 ? CountLeadingOnes_64(Imm)
696 : CountLeadingOnes_32(Imm);
735 uint64_t &Imm) {
773 Imm = 0;
775 Imm |= Mask
[all...] |
