| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
98 addOffset(const MachineInstrBuilder &MIB, int Offset) {
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
107 addRegOffset(const MachineInstrBuilder &MIB,
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
122 addFullAddress(const MachineInstrBuilder &MIB,
127 MIB.addReg(AM.Base.Reg)
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| Thumb1FrameLowering.cpp | 318 MachineInstrBuilder MIB =
321 AddDefaultPred(MIB);
322 MIB.copyImplicitOps(&*MBBI);
342 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH));
343 AddDefaultPred(MIB);
361 MIB.addReg(Reg, getKillRegState(isKill));
363 MIB.setMIFlags(MachineInstr::FrameSetup);
381 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
382 AddDefaultPred(MIB);
392 (*MIB).setDesc(TII.get(ARM::tPOP_RET))
[all...] |
| ARMBaseInstrInfo.cpp | 681 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
682 MIB.addReg(SrcReg, getKillRegState(KillSrc));
684 MIB.addReg(SrcReg, getKillRegState(KillSrc));
685 AddDefaultPred(MIB);
751 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB,
755 return MIB.addReg(Reg, State);
758 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
759 return MIB.addReg(Reg, State, SubIdx);
798 MachineInstrBuilder MIB =
802 MIB = AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI)
[all...] |
| Thumb2SizeReduction.cpp | 467 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
469 MIB.addOperand(MI->getOperand(0));
470 MIB.addOperand(MI->getOperand(1));
473 MIB.addImm(OffsetImm / Scale);
478 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
483 MIB.addOperand(MI->getOperand(OpNum));
486 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
489 MIB.setMIFlags(MI->getFlags());
491 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
528 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc()
[all...] |
| Thumb1RegisterInfo.cpp | 130 MachineInstrBuilder MIB =
133 MIB = AddDefaultT1CC(MIB);
135 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
137 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
138 AddDefaultPred(MIB);
242 const MachineInstrBuilder MIB =
245 AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
263 MIB = AddDefaultT1CC(MIB)
[all...] |
| ARMBaseInstrInfo.h | 320 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
321 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
325 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
326 return MIB.addReg(0);
330 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
332 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
336 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
337 return MIB.addReg(0);
|
| ARMInstrInfo.cpp | 125 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
129 MIB.addImm(0);
130 AddDefaultPred(MIB);
|
| ARMFastISel.cpp | 224 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
226 const MachineInstrBuilder &MIB,
272 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
273 MachineInstr *MI = &*MIB;
279 AddDefaultPred(MIB);
286 AddDefaultT1CC(MIB);
288 AddDefaultCC(MIB);
290 return MIB;
672 MachineInstrBuilder MIB;
675 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg
[all...] |
| MLxExpansionPass.cpp | 292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
296 MIB.addImm(LaneImm);
297 MIB.addImm(Pred).addReg(PredReg);
299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
304 MIB.addReg(TmpReg, getKillRegState(true))
307 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
309 MIB.addImm(Pred).addReg(PredReg);
|
| ARMFrameLowering.cpp | 223 MachineInstrBuilder MIB =
227 AddDefaultCC(AddDefaultPred(MIB));
447 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
449 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
453 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
458 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
628 MachineInstrBuilder MIB =
632 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
634 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
639 AddDefaultPred(MIB);
[all...] |
| Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
189 MachineBasicBlock::iterator InsertPos = MIB;
232 MIB.addImm(Mask);
|
| ARMLoadStoreOptimizer.cpp | 349 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(Opcode))
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc))
784 MIB.addOperand(MI->getOperand(OpNum));
787 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
[all...] |
| Thumb2InstrInfo.cpp | 279 MachineInstrBuilder MIB =
284 AddDefaultCC(MIB);
411 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
412 AddDefaultPred(MIB);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 207 MachineInstrBuilder &MIB,
226 MIB.addReg(VRBase, RegState::Define);
241 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
295 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
308 const MCInstrDesc &MCID = MIB->getDesc();
340 unsigned Idx = MIB->getNumOperands();
342 MIB->getOperand(Idx-1).isReg() &&
343 MIB->getOperand(Idx-1).isImplicit())
350 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill)
[all...] |
| InstrEmitter.h | 53 MachineInstrBuilder &MIB,
66 void AddRegisterOperand(MachineInstrBuilder &MIB,
77 void AddOperand(MachineInstrBuilder &MIB,
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
70 return &*MIB;
109 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
113 MIB.addReg(Cond[i].getReg());
115 MIB.addImm(Cond[i].getImm());
119 MIB.addMBB(TBB);
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 78 MachineInstrBuilder MIB(*MF, MI);
79 MIB.addReg(DstReg, RegState::Define);
80 MIB.addReg(AMDGPU::ALU_LITERAL_X);
81 MIB.addImm(Imm);
82 MIB.addReg(0); // PREDICATE_BIT
515 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
516 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
655 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
659 MIB.addImm(0) // $update_exec_mask
662 MIB.addImm(1) // $writ
[all...] |
| SIInstrInfo.cpp | 154 MachineInstrBuilder MIB(*MF, MI);
155 MIB.addReg(DstReg, RegState::Define);
156 MIB.addImm(Imm);
|
| /external/llvm/lib/CodeGen/ |
| MachineInstrBundle.cpp | 110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(),
112 Bundle.prepend(MIB);
191 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
200 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 213 MachineInstrBuilder MIB;
215 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
217 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
221 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
228 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
229 MIB.addReg(JumpTarget.getReg(), RegState::Kill);
235 MIB->addOperand(MBBI->getOperand(i));
|
| AArch64InstrInfo.cpp | 123 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE))
127 return &*MIB;
312 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
314 MIB.addOperand(Cond[i]);
315 MIB.addMBB(TBB);
319 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
321 MIB.addOperand(Cond[i]);
322 MIB.addMBB(TBB);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 59 MachineInstr::mop_iterator MIB = MBB->operands_begin();
62 for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) {
99 MachineBasicBlock::iterator MIB = MBB->begin();
121 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
171 for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) {
|
