| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 730 MVT RegVT = VA.getLocVT();
738 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
741 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
744 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 338 EVT RegVT = VA.getLocVT();
339 switch (RegVT.getSimpleVT().SimpleTy) {
344 << RegVT.getSimpleVT().SimpleTy << "\n";
351 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
357 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
360 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 268 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
274 MVT RegVT;
|
| SelectionDAGBuilder.cpp | 607 MVT regvt, EVT valuevt)
608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
[all...] |
| LegalizeVectorOps.cpp | 535 EVT RegVT = Value.getValueType();
536 EVT RegSclVT = RegVT.getScalarType();
|
| LegalizeDAG.cpp | 327 MVT RegVT =
332 unsigned RegBytes = RegVT.getSizeInBits() / 8;
336 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
349 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
371 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
453 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
455 unsigned RegBytes = RegVT.getSizeInBits() / 8;
459 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
469 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
487 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr
[all...] |
| LegalizeIntegerTypes.cpp | 708 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
710 // The argument is passed as NumRegs registers of type RegVT.
714 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
730 DAG.getConstant(i * RegVT.getSizeInBits(),
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 854 EVT RegVT = VA.getLocVT();
855 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
856 RegVT == MVT::i32 || RegVT == MVT::f32) {
860 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
861 } else if (RegVT == MVT::i64) {
865 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
