| /external/v8/src/arm/ |
| constants-arm.cc | 61 const char* Registers::names_[kNumRegisters] = {
67 // List of alias names which can be used when referring to ARM registers.
68 const Registers::RegisterAlias Registers::aliases_[] = {
79 const char* Registers::Name(int reg) {
90 // Support for VFP registers s0 to s31 (d0 to d15).
128 int Registers::Number(const char* name) {
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| constants-arm.h | 94 // Number of registers in normal ARM mode.
441 // These constants are declared in assembler-arm.cc, as they use named registers
738 class Registers {
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| simulator-arm.cc | 178 int regnum = Registers::Number(desc);
323 PrintF("%3s: 0x%08x %10d", Registers::Name(i), value, value);
440 int regnum = Registers::Number(arg1);
568 PrintF(" use register name 'all' to print all registers\n");
754 // All registers are initialized to zero to start with.
763 // Initializing VFP registers.
764 // All registers are initialized to zero to start with
766 // physical registers in the target.
875 // Simulator internal state for special registers such as PC.
[all...] |
| /external/smali/ |
| README.md | 15 - [Registers wiki page](https://code.google.com/p/smali/wiki/Registers)
|
| /external/v8/src/mips/ |
| constants-mips.cc | 39 // Registers.
44 const char* Registers::names_[kNumSimuRegisters] = {
61 // List of alias names which can be used when referring to MIPS registers.
62 const Registers::RegisterAlias Registers::aliases_[] = {
70 const char* Registers::Name(int reg) {
81 int Registers::Number(const char* name) {
109 // List of alias names which can be used when referring to MIPS registers.
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| simulator-mips.cc | 80 // Print all registers with a nice formatting.
222 int regnum = Registers::Number(desc);
281 #define REG_INFO(n) Registers::Name(n), GetRegisterValue(n), GetRegisterValue(n)
429 int regnum = Registers::Number(arg1);
557 int regnum = Registers::Number(arg1);
675 // Print registers and disassemble.
719 PrintF(" use register name 'all' to print all registers\n");
901 // All registers are initialized to zero to start with.
[all...] |
| constants-mips.h | 83 // Registers and FPURegisters.
85 // Number of general purpose registers.
89 // Number of registers with HI, LO, and pc.
95 // Number coprocessor registers.
99 // FPU (coprocessor 1) control registers. Currently only FCSR is implemented.
127 class Registers {
183 // the simulator will run through them and print the registers.
566 // registers and other constants.
|
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 124 // Also compute leading super-registers. Each register has a list of
125 // covered-by-subregs super-registers where it appears as the first explicit
133 // registers, so build a symmetric graph by adding links in both ends.
147 // Iterate over all register units in a set of registers.
230 // Map explicit sub-registers first, so the names take precedence.
231 // The inherited sub-registers are mapped below.
330 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
351 // sub-registers, the other registers won't contribute any more units.
354 // Explicit sub-registers are usually disjoint, so this is a good way o
[all...] |
| AsmWriterEmitter.cpp | 541 const std::vector<CodeGenRegister*> &Registers) {
543 SmallVector<std::string, 4> AsmNames(Registers.size());
544 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
545 const CodeGenRegister &Reg = *Registers[i];
584 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
597 const std::vector<CodeGenRegister*> &Registers =
611 O << " assert(RegNo && RegNo < " << (Registers.size()+1)
617 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers);
619 emitRegisterNameString(O, "", Registers);
[all...] |
| RegisterInfoEmitter.cpp | 38 // runEnums - Print out enum values for all of the registers.
70 // runEnums - Print out enum values for all of the registers.
73 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
76 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
78 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
95 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
96 OS << " " << Registers[i]->getName() << " = " <<
97 Registers[i]->EnumValue << ",\n";
98 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &
[all...] |
| CodeGenRegisters.h | 113 // Lazily compute a map of all sub-registers.
114 // This includes unique entries for all sub-sub-registers.
117 // Compute extra sub-registers by combining the existing sub-registers.
120 // Add this as a super-register to all sub-registers after the sub-register
125 assert(SubRegsComplete && "Must precompute sub-registers");
129 // Add sub-registers to OSet following a pre-order defined by the .td file.
141 // Get the list of super-registers in topological order, small to large.
142 // This is valid after computeSubRegs visits all registers during RegBank
145 assert(SubRegsComplete && "Must precompute sub-registers");
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| AsmMatcherEmitter.cpp | 186 /// For register classes, the records for all the registers in this class.
187 std::set<Record*> Registers;
209 // Registers classes are only related to registers classes, and only if
217 std::set_intersection(Registers.begin(), Registers.end(),
218 RHS.Registers.begin(), RHS.Registers.end(),
775 // Collect singleton registers, if used.
[all...] |
| /external/webrtc/src/common_audio/signal_processing/ |
| spl_sqrt_floor.s | 9 @ Registers touched: r1, r2
|
| /external/v8/tools/ |
| profile.js | 96 * Registers a library.
112 * Registers statically compiled code entry.
128 * Registers dynamic (JIT-compiled) code entry.
144 * Registers dynamic (JIT-compiled) code entry.
|
| /external/grub/netboot/ |
| 3c90x.c | 54 enum Registers
83 /** following are windowed registers **/
771 /** Program the MAC address into the station address registers **/
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 52 // Map of register aliases registers via the .req directive.
317 SmallVector<unsigned, 8> Registers;
356 // A vector register list is a sequential list of 1 to 4 registers.
465 Registers = o.Registers;
549 return Registers;
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| /external/openssl/crypto/bn/asm/ |
| pa-risc2.s | 37 ; For the floating point registers
39 ; "caller save" registers: fr4-fr11, fr22-fr31
40 ; "callee save" registers: fr12-fr21
41 ; "special" registers: fr0-fr3 (status and exception registers)
43 ; For the integer registers
45 ; "caller save" registers: r1,r19-r26
46 ; "callee save" registers: r3-r18
918 ; Registers to hold 64-bit values to manipulate. The "L" part
923 ; using them because they are callee save registers
[all...] |
| pa-risc2W.s | 31 ; For the floating point registers
33 ; "caller save" registers: fr4-fr11, fr22-fr31
34 ; "callee save" registers: fr12-fr21
35 ; "special" registers: fr0-fr3 (status and exception registers)
37 ; For the integer registers
39 ; "caller save" registers: r1,r19-r26
40 ; "callee save" registers: r3-r18
905 ; Registers to hold 64-bit values to manipulate. The "L" part
910 ; using them because they are callee save registers
[all...] |
| /external/robolectric/lib/main/ |
| sqlite-jdbc-3.7.2.jar | |
| /build/tools/droiddoc/templates-sac/assets/js/ |
| android_3p-bundle.js | [all...] |
| /build/tools/droiddoc/templates-sdk/assets/js/ |
| android_3p-bundle.js | [all...] |
