| /external/llvm/lib/Target/Hexagon/ |
| HexagonCallingConvLower.h | 111 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
113 if (!isAllocated(Regs[i]))
138 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
139 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
144 unsigned Reg = Regs[FirstUnalloc];
150 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs,
152 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
|
| /external/llvm/include/llvm/CodeGen/ |
| RegisterScavenging.h | 145 void setUsed(BitVector &Regs) {
146 RegsAvailable.reset(Regs);
148 void setUnused(BitVector &Regs) {
149 RegsAvailable |= Regs;
|
| CallingConvLower.h | 233 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const {
235 if (!isAllocated(Regs[i]))
260 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) {
261 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
266 unsigned Reg = Regs[FirstUnalloc];
272 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs,
274 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
279 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
|
| RegisterPressure.h | 211 void addLiveRegs(ArrayRef<unsigned> Regs);
312 void increaseRegPressure(ArrayRef<unsigned> Regs);
313 void decreaseRegPressure(ArrayRef<unsigned> Regs);
|
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 57 const std::vector<CodeGenRegister*> &Regs, bool isCtor);
59 const std::vector<CodeGenRegister*> &Regs,
76 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
173 const CodeGenRegister::Set &Regs = RC.getMembers();
174 if (Regs.empty())
179 OS << " {" << (*Regs.begin())->getWeight(RegBank)
311 const std::vector<CodeGenRegister*> &Regs,
319 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
320 Record *Reg = Regs[i]->TheDef;
338 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace")
[all...] |
| CodeGenRegisters.cpp | 153 RegUnitIterator(const CodeGenRegister::Set &Regs):
154 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() {
338 // SR is composed of multiple sub-regs. Find their names in this register.
[all...] |
| CodeGenTarget.cpp | 217 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName();
218 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name);
219 if (I == Regs.end())
|
| CodeGenRegisters.h | 644 // Compute the set of registers completely covered by the registers in Regs.
645 // The returned BitVector will have a bit set for each register in Regs,
647 // registers in Regs.
651 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
|
| AsmMatcherEmitter.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterPressure.cpp | 109 void RegPressureTracker::increaseRegPressure(ArrayRef<unsigned> Regs) {
110 for (unsigned I = 0, E = Regs.size(); I != E; ++I) {
111 if (TargetRegisterInfo::isVirtualRegister(Regs[I])) {
112 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I]);
119 TRI->getRegUnitPressureSets(Regs[I]),
120 TRI->getRegUnitWeight(Regs[I]));
126 void RegPressureTracker::decreaseRegPressure(ArrayRef<unsigned> Regs) {
127 for (unsigned I = 0, E = Regs.size(); I != E; ++I) {
128 if (TargetRegisterInfo::isVirtualRegister(Regs[I])) {
129 const TargetRegisterClass *RC = MRI->getRegClass(Regs[I])
[all...] |
| ExecutionDepsFix.cpp | 575 SmallVector<LiveReg, 4> Regs;
586 for (SmallVector<LiveReg, 4>::iterator i = Regs.begin(), e = Regs.end();
590 Regs.insert(i, LR);
594 Regs.push_back(LR);
600 while (!Regs.empty()) {
602 dv = Regs.pop_back_val().Value;
609 DomainValue *Latest = Regs.pop_back_val().Value;
|
| AggressiveAntiDepBreaker.h | 97 std::vector<unsigned> &Regs,
|
| AggressiveAntiDepBreaker.cpp | 70 std::vector<unsigned> &Regs,
75 Regs.push_back(Reg);
154 // Examine the live-in regs of all successors.
537 std::vector<unsigned> Regs;
538 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
539 assert(Regs.size() > 0 && "Empty register group!");
540 if (Regs.size() == 0)
550 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
551 unsigned Reg = Regs[i];
555 // If Reg has any references, then collect possible rename regs
[all...] |
| LocalStackSlotAllocation.cpp | 197 lookupCandidateBaseReg(const SmallVector<std::pair<unsigned, int64_t>, 8> &Regs,
203 unsigned e = Regs.size();
205 RegOffset = Regs[i];
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 590 SmallVector<std::pair<unsigned,bool>, 4> Regs;
622 Regs.push_back(std::make_pair(Reg, isKill));
625 if (Regs.empty())
627 if (Regs.size() > 1 || StrOpc== 0) {
631 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
632 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
633 } else if (Regs.size() == 1) {
636 .addReg(Regs[0].first, getKillRegState(Regs[0].second)
[all...] |
| ARMLoadStoreOptimizer.cpp | 97 ArrayRef<std::pair<unsigned, bool> > Regs,
279 /// registers in Regs as the register operands that would be loaded / stored.
287 ArrayRef<std::pair<unsigned, bool> > Regs,
290 unsigned NumRegs = Regs.size();
320 NewBase = Regs[NumRegs-1].first;
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
354 | getKillRegState(Regs[i].second));
393 SmallVector<std::pair<unsigned, bool>, 8> Regs;
400 Regs.push_back(std::make_pair(Reg, isKill));
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)
[all...] |
| Thumb2SizeReduction.cpp | 204 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
205 if (*Regs == ARM::CPSR)
621 // Early exit if the regs aren't all low regs.
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 186 SmallVector<SDValue, 4> Regs;
187 Regs.push_back(Val);
191 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
197 Regs.push_back(DAG.getUNDEF(VT));
200 Regs.data(), Regs.size()));
|
| R600InstrInfo.cpp | 574 std::vector<unsigned> Regs;
580 return Regs;
585 Regs.push_back(SuperReg);
588 Regs.push_back(Reg);
591 return Regs;
|
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 814 SmallPtrSet<const SCEV *, 16> &Regs,
826 SmallPtrSet<const SCEV *, 16> &Regs,
830 SmallPtrSet<const SCEV *, 16> &Regs,
840 SmallPtrSet<const SCEV *, 16> &Regs,
862 if (!Regs.count(AR->getOperand(1))) {
863 RateRegister(AR->getOperand(1), Regs, L, SE, DT);
886 /// that refers to one of those regs an instant loser.
888 SmallPtrSet<const SCEV *, 16> &Regs,
896 if (Regs.insert(Reg)) {
897 RateRegister(Reg, Regs, L, SE, DT)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | 598 /// Regs - This list holds the registers assigned to the values.
602 SmallVector<unsigned, 4> Regs;
606 RegsForValue(const SmallVector<unsigned, 4> ®s,
608 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
619 Regs.push_back(Reg + i);
639 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT)
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
