| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.h | 28 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| ARMInstrInfo.h | 28 explicit ARMInstrInfo(const ARMSubtarget &STI);
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| ARMHazardRecognizer.h | 33 const ARMSubtarget &STI;
42 const ARMSubtarget &sti,
45 TRI(tri), STI(sti), LastMI(0) {}
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| Thumb2RegisterInfo.h | 28 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
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| Thumb1InstrInfo.h | 27 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.h | 31 MBlazeDisassembler(const MCSubtargetInfo &STI) :
32 MCDisassembler(STI) {
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| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 56 MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0),
58 STI(STI), CommentStream(0) {}
100 const MCSubtargetInfo &STI;
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| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.h | 26 const MipsSubtarget &STI;
29 explicit MipsFrameLowering(const MipsSubtarget &sti)
30 : TargetFrameLowering(StackGrowsDown, sti.hasMips64() ? 16 : 8, 0,
31 sti.hasMips64() ? 16 : 8), STI(sti) {}
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| MipsSEFrameLowering.h | 23 explicit MipsSEFrameLowering(const MipsSubtarget &STI)
24 : MipsFrameLowering(STI) {}
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| Mips16FrameLowering.h | 22 explicit Mips16FrameLowering(const MipsSubtarget &STI)
23 : MipsFrameLowering(STI) {}
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| MipsSEFrameLowering.cpp | 40 return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I];
53 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
54 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
55 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
56 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
106 if (!STI.isLittle())
121 const TargetRegisterClass *RC = STI.isABI_N64() ?
169 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
170 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
171 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.h | 25 const MBlazeSubtarget &STI;
28 explicit MBlazeFrameLowering(const MBlazeSubtarget &sti)
29 : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) {
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 34 const MCSubtargetInfo &STI,
39 const MCSubtargetInfo &STI,
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| AMDGPUMCTargetDesc.cpp | 70 const MCSubtargetInfo &STI) {
76 const MCSubtargetInfo &STI,
78 if (STI.getFeatureBits() & AMDGPU::Feature64BitPtr) {
79 return createSIMCCodeEmitter(MCII, MRI, STI, Ctx);
81 return createR600MCCodeEmitter(MCII, MRI, STI, Ctx);
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| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 37 const TargetSubtargetInfo *STI;
44 TargetSchedModel(): STI(0), TII(0) {}
51 void init(const MCSchedModel &sm, const TargetSubtargetInfo *sti,
110 return STI->getWriteProcResBegin(SC);
113 return STI->getWriteProcResEnd(SC);
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| /external/llvm/tools/llvm-mc/ |
| Disassembler.h | 33 MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 21 const HexagonSubtarget &STI;
25 explicit HexagonFrameLowering(const HexagonSubtarget &sti)
26 : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) {
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| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 26 const MSP430Subtarget &STI;
29 explicit MSP430FrameLowering(const MSP430Subtarget &sti)
30 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) {
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| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 36 MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
38 MCDisassembler(STI), RegInfo(Info), isBigEndian(bigEndian) {}
55 MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
57 MipsDisassemblerBase(STI, Info, bigEndian) {}
74 Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
76 MipsDisassemblerBase(STI, Info, bigEndian) {}
198 const MCSubtargetInfo &STI) {
199 return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
204 const MCSubtargetInfo &STI) {
205 return new MipsDisassembler(STI, T.createMCRegInfo(""), false)
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.h | 40 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCTargetDesc.h | 35 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.h | 39 const MCSubtargetInfo &STI,
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| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.h | 109 X86GenericDisassembler(const MCSubtargetInfo &STI, DisassemblerMode mode,
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| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 55 const TargetSubtargetInfo *sti,
58 STI = sti;
60 STI->initInstrItins(InstrItins);
138 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
218 STI->getWriteLatencyEntry(SCDesc, DefIdx);
229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
263 STI->getWriteLatencyEntry(SCDesc, DefIdx);
301 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
302 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.h | 40 const AArch64Subtarget &STI;
43 explicit AArch64FrameLowering(const AArch64Subtarget &sti)
45 STI(sti) {
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