/external/qemu/target-mips/ |
exec.h | 68 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | 73 !(env->hflags & MIPS_HFLAG_DM)) { 74 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU; 77 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || 80 env->hflags |= MIPS_HFLAG_64; 82 env->hflags |= MIPS_HFLAG_UX; 85 !(env->hflags & MIPS_HFLAG_KSU)) 86 env->hflags |= MIPS_HFLAG_CP0; 88 env->hflags |= MIPS_HFLAG_FPU; 90 env->hflags |= MIPS_HFLAG_F64 [all...] |
helper.c | 113 int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; 114 int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; 124 qemu_log("user mode %d h %08x\n", user_mode, env->hflags); 358 saved_hflags = env->hflags; 366 env->hflags = MIPS_HFLAG_KM; 404 env->hflags = saved_hflags; 434 env->hflags = saved_hflags; 603 (env->hflags & MIPS_HFLAG_DM)) 630 if (env->hflags & MIPS_HFLAG_BMASK) { 634 env->hflags &= ~MIPS_HFLAG_BMASK [all...] |
cpu.h | 416 uint32_t hflags; /* CPU State */ member in struct:CPUMIPSState 420 /* The KSU flags must be the lowest bits in hflags. The flag order 492 hflags layout. */ 499 return env->hflags & MIPS_HFLAG_KSU; 529 (env->hflags & MIPS_HFLAG_DM)) { 638 env->hflags &= ~MIPS_HFLAG_BMASK; 639 env->hflags |= tb->flags & MIPS_HFLAG_BMASK; 647 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
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translate.c | 433 static TCGv_i32 hflags; variable 469 uint32_t hflags, saved_hflags; member in struct:DisasContext 617 if (ctx->hflags & MIPS_HFLAG_F64) { 632 if (ctx->hflags & MIPS_HFLAG_F64) { 753 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); 758 if (ctx->hflags != ctx->saved_hflags) { 759 tcg_gen_movi_i32(hflags, ctx->hflags); 760 ctx->saved_hflags = ctx->hflags; 8232 int hflags = ctx->hflags & MIPS_HFLAG_BMASK; local [all...] |
op_helper.c | 48 !(env->hflags & MIPS_HFLAG_DM) && 750 if (env->hflags & MIPS_HFLAG_DM) 1168 switch (env->hflags & MIPS_HFLAG_KSU) { [all...] |
machine.c | 84 qemu_put_be32s(f, &env->hflags); 235 qemu_get_be32s(f, &env->hflags);
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/external/qemu/hw/ |
mips_int.c | 12 !(env->hflags & MIPS_HFLAG_DM)) {
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pc.c | 132 i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1); [all...] |
/external/qemu/target-i386/ |
cpu.h | 579 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags member in struct:CPUX86State 714 cache: it synchronizes the hflags with the segment cache values */ 734 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) { 736 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 737 env->hflags &= ~(HF_ADDSEG_MASK); 744 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) | 750 if (env->hflags & HF_CS64_MASK) { 754 !(env->hflags & HF_CS32_MASK)) { 767 env->hflags = (env->hflags [all...] |
machine.c | 29 uint32_t hflags; local 39 hflags = env->hflags; /* XXX: suppress most of the redundant hflags */ 40 qemu_put_be32s(f, &hflags); 192 uint32_t hflags; local 202 qemu_get_be32s(f, &hflags); 364 /* XXX: compute redundant hflags bits */ 365 env->hflags = hflags; [all...] |
hax-all.c | 788 uint32_t hflags; local 790 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 791 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 792 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 794 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 795 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << 799 hflags |= HF_LMA_MASK; 802 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 803 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 805 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) > [all...] |
kvm.c | 499 uint32_t hflags; local 543 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 544 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 545 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 547 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 548 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) << 552 hflags |= HF_LMA_MASK; 555 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 556 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 558 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) > [all...] |
helper.c | 484 env->hflags |= HF_SOFTMMU_MASK; 606 if (env->hflags & HF_CS64_MASK) { 616 if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) 647 cpu_fprintf(f, sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] 673 if (env->hflags & HF_CS64_MASK) { 704 env->hflags & HF_CPL_MASK, 705 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, 707 (env->hflags >> HF_SMM_SHIFT) & 1, 731 env->hflags & HF_CPL_MASK, 732 (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1 [all...] |
exec.h | 366 /* load efer and update the corresponding hflags. XXX: do consistency 371 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK); 373 env->hflags |= HF_LMA_MASK; 375 env->hflags |= HF_SVME_MASK;
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op_helper.c | 234 cpl = env->hflags & HF_CPL_MASK; 428 env->hflags |= HF_TS_MASK; 718 cpl = env->hflags & HF_CPL_MASK; 918 cpl = env->hflags & HF_CPL_MASK; 1016 if (env->hflags & HF_LMA_MASK) { 1022 code64 = env->hflags & HF_CS64_MASK; [all...] |
/external/qemu/ |
kqemu.c | 517 if (env->hflags & HF_LMA_MASK) { 523 code64 = env->hflags & HF_CS64_MASK; 744 cpl = (env->hflags & HF_CPL_MASK); 825 if ((env->hflags & HF_LMA_MASK) && 839 !(env->hflags & HF_CS32_MASK)) { 853 env->hflags = (env->hflags & 858 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) | 861 env->hflags |= HF_OSFXSR_MASK [all...] |
cpu-exec.c | 419 !(env->hflags & HF_SMM_MASK)) { 439 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 457 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { [all...] |
exec.c | [all...] |