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  /external/webkit/Source/JavaScriptCore/assembler/
ARMAssembler.cpp 95 ARMWord imm1; local
132 imm1 = OP2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8);
135 imm1 = OP2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
169 imm1 = OP2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
190 mov_r(reg, imm1);
193 mvn_r(reg, imm1);
  /external/webkit/Source/JavaScriptCore/dfg/
DFGNode.h 199 Node(NodeType op, ExceptionInfo exceptionInfo, OpInfo imm1, OpInfo imm2, NodeIndex child1 = NoNode, NodeIndex child2 = NoNode, NodeIndex child3 = NoNode)
207 , m_opInfo(imm1.m_value)
DFGSpeculativeJIT.cpp 368 int32_t imm1; local
369 if (isDoubleConstantWithInt32Value(node.child1, imm1)) {
374 speculationCheck(m_jit.branchAdd32(MacroAssembler::Overflow, reg, Imm32(imm1), result.registerID()));
  /external/valgrind/main/VEX/priv/
host_ppc_defs.c     [all...]
guest_arm_toIR.c 2613 UInt imm1 = SLICE_UInt(i0,10,10); local
    [all...]

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