/external/linux-tools-perf/util/include/linux/ |
prefetch.h | 4 static inline void prefetch(void *a __attribute__((unused))) { } function
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list.h | 4 #include <linux/prefetch.h> 8 #include "prefetch.h"
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/external/kernel-headers/original/asm-generic/ |
xor.h | 309 prefetch(p2); 313 prefetch(p2+8); 336 prefetch(p2); 337 prefetch(p3); 341 prefetch(p2+8); 342 prefetch(p3+8); 367 prefetch(p2); 368 prefetch(p3); 369 prefetch(p4); 373 prefetch(p2+8) [all...] |
/external/iptables/libiptc/ |
linux_list.h | 30 #define prefetch(x) 1 macro 339 for (pos = (head)->next, prefetch(pos->next); pos != (head); \ 340 pos = pos->next, prefetch(pos->next)) 361 for (pos = (head)->prev, prefetch(pos->prev); pos != (head); \ 362 pos = pos->prev, prefetch(pos->prev)) 382 prefetch(pos->member.next); \ 385 prefetch(pos->member.next)) 395 prefetch(pos->member.prev); \ 398 prefetch(pos->member.prev)) 419 prefetch(pos->member.next); [all...] |
/packages/apps/Browser/src/com/android/browser/preferences/ |
BandwidthPreferencesFragment.java | 54 // set default value for link prefetch setting 55 ListPreference prefetch = (ListPreference) prefScreen.findPreference( local 57 if (prefetch != null) { 58 prefetch.setValue(BrowserSettings.getInstance().getDefaultLinkPrefetchSetting());
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/external/kernel-headers/original/asm-arm/ |
processor.h | 107 #define prefetch(ptr) \ macro 117 #define prefetchw(ptr) prefetch(ptr)
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/external/kernel-headers/original/linux/ |
list.h | 8 #include <linux/prefetch.h> 362 for (pos = (head)->next; prefetch(pos->next), pos != (head); \ 384 for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ 405 prefetch(pos->member.next), &pos->member != (head); \ 416 prefetch(pos->member.prev), &pos->member != (head); \ 441 prefetch(pos->member.next), &pos->member != (head); \ 453 for (; prefetch(pos->member.next), &pos->member != (head); \ 527 prefetch(rcu_dereference(pos)->next), pos != (head); \ 564 prefetch(rcu_dereference(pos)->member.next), \ 582 prefetch(rcu_dereference((pos))->next), (pos) != (head); [all...] |
/external/openssl/crypto/sha/asm/ |
sha1-s390x.pl | 50 $ctx="%r2"; $prefetch="%r2"; 71 lg $prefetch,$stdframe($sp) ### Xupdate(16) warm-up 80 xgr $X[0],$prefetch ### Xupdate($i) 81 lg $prefetch,`$stdframe+4*(($i+2)%16)`($sp) 83 xgr $X[0],$prefetch
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sha256-mips.S | 779 lw $8,0($29) # prefetch from ring buffer 832 lw $9,4($29) # prefetch from ring buffer 883 lw $10,8($29) # prefetch from ring buffer 951 lw $11,12($29) # prefetch from ring buffer 1016 lw $12,16($29) # prefetch from ring buffer 1081 lw $13,20($29) # prefetch from ring buffer 1146 lw $14,24($29) # prefetch from ring buffer 1211 lw $15,28($29) # prefetch from ring buffer 1276 lw $16,32($29) # prefetch from ring buffer 1341 lw $17,36($29) # prefetch from ring buffe [all...] |
/external/linux-tools-perf/util/include/linux/added/ |
list.h | 351 for (pos = (head)->next; prefetch(pos->next), pos != (head); \ 373 for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ 394 prefetch(pos->prev), pos != (head); \ 405 prefetch(pos->member.next), &pos->member != (head); \ 416 prefetch(pos->member.prev), &pos->member != (head); \ 441 prefetch(pos->member.next), &pos->member != (head); \ 455 prefetch(pos->member.prev), &pos->member != (head); \ 467 for (; prefetch(pos->member.next), &pos->member != (head); \ 635 for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \ 651 pos && ({ prefetch(pos->next); 1;}) && [all...] |
/external/yaffs2/yaffs2/ |
devextras.h | 54 #define prefetch(x) 1 macro 193 for (pos = (head)->next, prefetch(pos->next); pos != (head); \ 194 pos = pos->next, prefetch(pos->next))
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/external/kernel-headers/original/asm-mips/ |
processor.h | 21 #include <asm/prefetch.h> 251 static inline void prefetch(const void *addr) function
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/external/oprofile/events/mips/r12000/ |
events | 20 event:0x10 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_INSTRUCTIONS_EXECUTED : Executed prefetch instructions 21 event:0x11 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instructions 34 event:0x1e counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_TO_CLEAN_SC_BLOCK : Store/prefetch exclusive to clean block in secondary cache 35 event:0x1f counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_SHARED_SC_BLOCK : Store/prefetch exclusive to shared block in secondary
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/external/llvm/test/MC/X86/ |
3DNow.s | 73 // CHECK: prefetch (%rax) # encoding: [0x0f,0x0d,0x00] 75 prefetch (%rax) label
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/external/oprofile/events/mips/vr5432/ |
events | 6 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
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/external/oprofile/events/mips/vr5500/ |
events | 8 event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction
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/bionic/libc/kernel/arch-mips/asm/ |
processor.h | 29 #include <asm/prefetch.h>
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/development/ndk/platforms/android-9/arch-mips/include/asm/ |
processor.h | 29 #include <asm/prefetch.h>
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/prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
processor.h | 29 #include <asm/prefetch.h>
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/prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
processor.h | 29 #include <asm/prefetch.h>
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/external/clang/test/CodeGen/ |
builtins.c | 29 V(prefetch, (&N)); 30 V(prefetch, (&N, 1)); 31 V(prefetch, (&N, 1, 0));
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/external/oprofile/events/i386/atom/ |
events | 15 event:0x07 counters:0,1 um:simd_prefetch minimum:6000 name:PREFETCH : Streaming SIMD Extensions (SSE) Prefetch instructions executed 25 event:0x24 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_IN : L2 cache misses 27 event:0x26 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_OUT : L2 cache lines evicted 28 event:0x27 counters:0,1 um:core,prefetch minimum:500 name:L2_M_LINES_OUT : Modified lines evicted from the L2 cache 30 event:0x29 counters:0,1 um:core,prefetch,mesi minimum:6000 name:L2_LD : L2 cache reads 33 event:0x2E counters:0,1 um:l2_rqsts,core,prefetch,mesi minimum:6000 name:L2_RQSTS : L2 cache requests 34 event:0x30 counters:0,1 um:core,prefetch,mesi minimum:500 name:L2_REJECT_BUSQ : Rejected L2 cache requests
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/external/oprofile/events/i386/westmere/ |
unit_masks | 115 0x01 requests L1D hardware prefetch requests 116 0x02 miss L1D hardware prefetch misses 117 0x04 triggers L1D hardware prefetch requests triggered 148 0x04 prefetch_clean L2 lines evicted by a prefetch request 149 0x08 prefetch_dirty L2 modified lines evicted by a prefetch request 161 0x40 prefetch_hit L2 prefetch hits 162 0x80 prefetch_miss L2 prefetch misses 170 0x08 prefetch L2 prefetch transactions
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/external/oprofile/events/i386/nehalem/ |
unit_masks | 90 0x40 prefetch_hit Counts L2 prefetch hits for both code and data 91 0x80 prefetch_miss Counts L2 prefetch misses for both code and data 101 0x10 i_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i 102 0x20 s_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state 103 0x40 e_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state 104 0x80 m_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state 105 0xF0 mesi Counts all L2 prefetch requests 162 0x01 nta Counts number of SSE NTA prefetch/weakly-ordered instructions which missed the L1 data cache 165 0x01 requests Counts number of hardware prefetch requests dispatched out of the prefetch FIF [all...] |
/external/oprofile/events/mips/r10000/ |
events | 9 event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued 10 event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
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