/prebuilts/ndk/4/platforms/android-5/arch-x86/usr/include/asm/ |
msr.h | 32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2)) macro 34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 46 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 48 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/prebuilts/ndk/4/platforms/android-8/arch-x86/usr/include/asm/ |
msr.h | 32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2)) macro 34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 46 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 48 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/prebuilts/ndk/6/platforms/android-9/arch-x86/usr/include/asm/ |
msr.h | 32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2)) macro 34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 46 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 48 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/prebuilts/ndk/7/platforms/android-14/arch-x86/usr/include/asm/ |
msr.h | 32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2)) macro 34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 46 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 48 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/prebuilts/ndk/7/platforms/android-9/arch-x86/usr/include/asm/ |
msr.h | 32 #define wrmsr(msr,val1,val2) __asm__ __volatile__("wrmsr" : : "c" (msr), "a" (val1), "d" (val2)) macro 34 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 46 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 48 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/asm/ |
msr.h | 36 #define wrmsr(msr,val1,val2) \ macro 37 __asm__ __volatile__("wrmsr" \ 41 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 64 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 66 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
msr.h | 36 #define wrmsr(msr,val1,val2) \ macro 37 __asm__ __volatile__("wrmsr" \ 41 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 64 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 66 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/asm/ |
msr.h | 36 #define wrmsr(msr,val1,val2) \ macro 37 __asm__ __volatile__("wrmsr" \ 41 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 64 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 66 #define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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/external/kernel-headers/original/asm-x86/ |
msr.h | 47 asm volatile("wrmsr" : : "c" (msr), "A"(val)); 54 asm volatile("2: wrmsr ; xorl %0,%0\n" 100 static inline void wrmsr(u32 __msr, u32 __low, u32 __high) function 110 /* wrmsr with exception handling */ 132 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 154 wrmsr(msr_no, l, h); 191 #define wrmsr(msr,val1,val2) \ macro 192 __asm__ __volatile__("wrmsr" \ 196 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32) 219 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2 [all...] |
paravirt.h | 116 err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ 577 #define wrmsr(msr,val1,val2) do { \ macro 586 #define wrmsrl(msr,val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) 616 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
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processor_32.h | 507 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
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/external/oprofile/module/x86/ |
op_model_p4.c | 362 #define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high));} while (0) 373 #define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high));} while (0) 378 #define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1);} while (0) 566 wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high); 574 wrmsr(p4_unused_cccr[i], low, high); 580 wrmsr(addr, 0, 0); 585 wrmsr(MSR_P4_IQ_ESCR0, 0, 0); 586 wrmsr(MSR_P4_IQ_ESCR1, 0, 0); 591 wrmsr(addr, 0, 0); 596 wrmsr(addr, 0, 0) [all...] |
op_apic.c | 122 wrmsr(MSR_IA32_APICBASE, msr_low | (1 << 11), msr_high); 145 wrmsr(MSR_IA32_APICBASE, msr_low & ~(1 << 11), msr_high);
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op_model_athlon.c | 21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), 0xffff);} while (0) 25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls.addrs[(c)], (l), (h));} while (0)
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op_model_ppro.c | 21 #define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters.addrs[(c)], -(u32)(l), -1);} while (0) 25 #define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls.addrs[(c)]), (l), (h));} while (0)
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op_msr.h | 16 * magically cloberred by wrmsr */ 18 #undef wrmsr macro 19 #define wrmsr(msr, val1, val2) \ macro 20 __asm__ __volatile__("wrmsr" \
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op_nmi.c | 251 wrmsr(controls->addrs[i], 259 wrmsr(counters->addrs[i],
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/external/qemu-pc-bios/bochs/bios/ |
rombios32start.S | 61 wrmsr
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rombios32.c | 165 static void wrmsr(unsigned index, uint64_t val) function 167 asm volatile ("wrmsr" : : "c"(index), "A"(val)); 462 wrmsr(index, val); [all...] |
/external/qemu/target-i386/ |
helper.h | 85 DEF_HELPER_0(wrmsr, void)
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/external/valgrind/main/perf/ |
tinycc.c | [all...] |
/external/llvm/test/MC/X86/ |
x86-32-coverage.s | [all...] |