/external/llvm/lib/Target/Mips/ |
MipsSEFrameLowering.cpp | 96 unsigned Reg = I->getReg(); 98 // If Reg is a double precision register, emit two cfa_offsets, 100 if (Mips::AFGR64RegClass.contains(Reg)) { 103 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven)); 104 MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd)); 112 // Reg is either in CPURegs or FGR32. 114 SrcML = MachineLocation(Reg); 227 unsigned Reg = CSI[i].getReg(); 228 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64 [all...] |
MipsSEInstrInfo.cpp | 63 /// the source reg along with the FrameIndex of the loaded stack slot. If 91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. 103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg. 121 else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg. 131 else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 267 unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0); 268 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 273 /// result of adding register REG and immediate IMM. 297 unsigned Reg = RegInfo.createVirtualRegister(RC); 300 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)) [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | 426 llvm_unreachable("Impossible reg-to-reg copy"); 498 unsigned Reg = 0; 501 Reg = PPC::CR0; 504 Reg = PPC::CR1; 507 Reg = PPC::CR2; 510 Reg = PPC::CR3; 513 Reg = PPC::CR4; 516 Reg = PPC::CR5; 519 Reg = PPC::CR6 [all...] |
PPCRegisterInfo.cpp | 210 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 213 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 217 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 221 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 230 .addReg(Reg, RegState::Kill) 245 .addReg(Reg, RegState::Kill) 289 unsigned Reg = LP64 ? PPC::X0 : PPC::R0; 294 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg) 301 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 302 .addReg(Reg, RegState::Kill [all...] |
/external/llvm/lib/Target/R600/ |
AMDGPUIndirectAddressing.cpp | 37 bool regHasExplicitDef(MachineRegisterInfo &MRI, unsigned Reg) const; 166 unsigned Reg = *LJ; 167 if (RegisterAddressMap.find(Reg) == RegisterAddressMap.end()) { 171 if (RegisterAddressMap[Reg] == Address) { 172 PhiRegisters.push_back(Reg); 194 unsigned Reg = *RI; 195 MachineInstr *DefInst = MRI.getVRegDef(Reg); 198 Phi.addReg(Reg); 200 MBB.removeLiveIn(Reg); 223 unsigned Reg = MO.getReg() [all...] |
SIInsertWaits.cpp | 139 unsigned Reg = Op.getReg(); 140 unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize(); 184 unsigned Reg = Op.getReg(); 185 unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize(); 190 Result.first = TRI.getEncodingValue(Reg);
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SILowerControlFlow.cpp | 179 unsigned Reg = MI.getOperand(0).getReg(); 182 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) 185 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) 187 .addReg(Reg); 275 unsigned Reg = MI.getOperand(0).getReg(); 280 .addReg(Reg);
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/external/llvm/lib/Target/X86/ |
X86AsmPrinter.cpp | 217 // pc-relativeness was handled when computing the value in the reg. 243 unsigned Reg = MO.getReg(); 248 Reg = getX86SubSuperRegister(Reg, VT); 250 O << X86ATTInstPrinter::getRegisterName(Reg); 381 unsigned Reg = MO.getReg(); 385 Reg = getX86SubSuperRegister(Reg, MVT::i8); 388 Reg = getX86SubSuperRegister(Reg, MVT::i8, true) [all...] |
X86MCInstLower.cpp | 231 unsigned Reg = MI->getOperand(OpNo).getReg(); 232 if (Reg != 0) 233 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32)); 241 unsigned Reg = MI->getOperand(OpNo+i).getReg(); 243 if (Reg == 0 || Reg == X86::RIP) continue; 245 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64)); 272 unsigned Reg = Inst.getOperand(0).getReg(); 273 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 212 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo); 213 Inst.addOperand(MCOperand::CreateReg(Reg));
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/external/llvm/lib/Target/XCore/ |
XCoreFrameLowering.cpp | 202 unsigned Reg = CSI.getReg(); 204 MachineLocation CSSrc(Reg); 291 unsigned Reg = it->getReg(); 292 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 293 TII.storeRegToStackSlot(MBB, MI, Reg, true, 317 unsigned Reg = it->getReg(); 318 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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/external/llvm/utils/TableGen/ |
CodeGenTarget.cpp | 226 const CodeGenRegister *Reg = getRegBank().getReg(R); 231 if (RC.contains(Reg)) {
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DAGISelMatcherEmitter.cpp | 438 const CodeGenRegister *Reg = Matcher->getReg(); 441 if (Reg && Reg->EnumValue > 255) { 443 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n"; 447 if (Reg) { 448 OS << getQualifiedName(Reg->TheDef) << ",\n";
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/external/llvm/include/llvm/CodeGen/ |
CallingConvLower.h | 191 bool isAllocated(unsigned Reg) const { 192 return UsedRegs[Reg/32] & (1 << (Reg&31)); 243 unsigned AllocateReg(unsigned Reg) { 244 if (isAllocated(Reg)) return 0; 245 MarkAllocated(Reg); 246 return Reg; 250 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { 251 if (isAllocated(Reg)) return 0; 252 MarkAllocated(Reg); [all...] |
/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | 76 bool contains(unsigned Reg) const { 77 return MC->contains(Reg); 160 /// For all Reg in SuperRC: 161 /// this->contains(Reg:Idx) 225 // Pointer to array of lane masks, one per sub-reg index. 252 /// returns true if Reg is in the range used for stack slots. 258 static bool isStackSlot(unsigned Reg) { 259 return int(Reg) >= (1 << 30); 264 static int stackSlot2Index(unsigned Reg) { 265 assert(isStackSlot(Reg) && "Not a stack slot") [all...] |
/external/llvm/lib/CodeGen/ |
LiveVariables.cpp | 131 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, 133 assert(MRI->getVRegDef(reg) && "Register use before def!"); 137 VarInfo& VRInfo = getVarInfo(reg); 168 if (MBB == MRI->getVRegDef(reg)->getParent()) return; 179 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI); 182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { 183 VarInfo &VRInfo = getVarInfo(Reg); 192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { 219 if (TRI->isSubRegister(Reg, DefReg)) [all...] |
MachineCSE.cpp | 81 bool isPhysDefTriviallyDead(unsigned Reg, 94 bool isProfitableToCSE(unsigned CSReg, unsigned Reg, 121 unsigned Reg = MO.getReg(); 122 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 124 if (!MRI->hasOneNonDBGUse(Reg)) 128 MachineInstr *DefMI = MRI->getVRegDef(Reg); 136 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg))) 151 MachineCSE::isPhysDefTriviallyDead(unsigned Reg, 167 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) 171 if (!TRI->regsOverlap(MO.getReg(), Reg)) [all...] |
PHIElimination.cpp | 85 bool isLiveIn(unsigned Reg, MachineBasicBlock *MBB); 86 bool isLiveOutPastPHIs(unsigned Reg, MachineBasicBlock *MBB); 228 assert(MPhi->getOperand(0).getSubReg() == 0 && "Can't handle sub-reg PHIs"); 553 unsigned Reg = BBI->getOperand(i).getReg(); 573 if (!isLiveOutPastPHIs(Reg, PreMBB) && !SplitAllCriticalEdges) 576 DEBUG(dbgs() << PrintReg(Reg) << " live-out before critical edge BB#" 580 // If Reg is not live-in to MBB, it means it must be live-in to some 584 // If Reg *is* live-in to MBB, the interference is inevitable and a copy 588 bool ShouldSplit = !isLiveIn(Reg, &MBB) || SplitAllCriticalEdges; 616 bool PHIElimination::isLiveIn(unsigned Reg, MachineBasicBlock *MBB) [all...] |