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  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.cpp 25 #include "llvm/ADT/BitVector.h"
61 BitVector
63 BitVector Reserved(getNumRegs());
AArch64RegisterInfo.h 40 BitVector getReservedRegs(const MachineFunction &MF) const;
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.cpp 20 #include "llvm/ADT/BitVector.h"
77 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
78 BitVector Reserved(getNumRegs());
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.cpp 19 #include "llvm/ADT/BitVector.h"
117 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
118 BitVector Reserved(getNumRegs());
  /external/llvm/lib/Target/R600/
AMDILDevice.h 20 #include "llvm/ADT/BitVector.h"
107 BitVector mHWBits;
108 llvm::BitVector mSWBits;
R600RegisterInfo.h 32 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 17 #include "llvm/ADT/BitVector.h"
42 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
43 BitVector Reserved(getNumRegs());
  /external/llvm/lib/CodeGen/
TargetRegisterInfo.cpp 15 #include "llvm/ADT/BitVector.h"
121 const TargetRegisterClass *RC, BitVector &R){
128 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
130 BitVector Allocatable(getNumRegs());
144 BitVector Reserved = getReservedRegs(MF);
AggressiveAntiDepBreaker.h 21 #include "llvm/ADT/BitVector.h"
126 BitVector CriticalPathSet;
177 BitVector GetRenameRegisters(unsigned Reg);
AggressiveAntiDepBreaker.cpp 128 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
171 BitVector Pristine = MFI->getPristineRegs(BB);
493 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
494 BitVector BV(TRI->getNumRegs(), false);
511 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
544 // collect the BitVector of registers that can be used to rename
548 std::map<unsigned, BitVector> RenameRegisterMap;
559 BitVector BV = GetRenameRegisters(Reg);
560 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
645 BitVector BV = RenameRegisterMap[Reg]
    [all...]
  /dalvik/vm/analysis/
Liveness.cpp 25 BitVector* workBits);
28 const BitVector* workBits);
65 BitVector* workBits;
183 BitVector* lineBits = vdata->registerLines[curIdx].liveRegs;
283 static inline void GEN(BitVector* workBits, u4 regIndex)
291 static inline void GENW(BitVector* workBits, u4 regIndex)
300 static inline void KILL(BitVector* workBits, u4 regIndex)
308 static inline void KILLW(BitVector* workBits, u4 regIndex)
320 BitVector* workBits)
757 BitVector* liveRegs = vdata->registerLines[idx].liveRegs
    [all...]
  /external/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 19 #include "llvm/ADT/BitVector.h"
101 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg,
105 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
108 BitVector Defs, Uses;
317 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
330 BitVector AllocSet = TRI.getAllocatableSet(MF);
353 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs());
369 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses
    [all...]
MipsRegisterInfo.cpp 22 #include "llvm/ADT/BitVector.h"
103 BitVector MipsRegisterInfo::
113 BitVector Reserved(getNumRegs());
MipsRegisterInfo.h 50 BitVector getReservedRegs(const MachineFunction &MF) const;
  /external/marisa-trie/v0_1_5/lib/
Makefile.in 80 reader.lo writer.lo intvector.lo bitvector.lo tail.lo trie.lo \
232 marisa_alpha/bitvector.cc \
259 marisa_alpha/bitvector.h \
339 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bitvector.Plo@am__quote@
414 bitvector.lo: marisa_alpha/bitvector.cc
415 @am__fastdepCXX_TRUE@ $(LIBTOOL) --tag=CXX $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -MT bitvector.lo -MD -MP -MF $(DEPDIR)/bitvector.Tpo -c -o bitvector.lo `test -f 'marisa_alpha/bitvector.cc' || echo '$(srcdir)/'`marisa_alpha/bitvector.c
    [all...]
  /external/llvm/lib/Target/MBlaze/
MBlazeRegisterInfo.cpp 21 #include "llvm/ADT/BitVector.h"
70 BitVector MBlazeRegisterInfo::
72 BitVector Reserved(getNumRegs());
MBlazeRegisterInfo.h 51 BitVector getReservedRegs(const MachineFunction &MF) const;
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 17 #include "llvm/ADT/BitVector.h"
72 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
73 BitVector Reserved(getNumRegs());
XCoreRegisterInfo.h 49 BitVector getReservedRegs(const MachineFunction &MF) const;
  /dalvik/vm/
Dalvik.h 27 #include "BitVector.h"
  /external/llvm/include/llvm/ADT/
SparseBitVector.h 1 //===- llvm/ADT/SparseBitVector.h - Efficient Sparse BitVector -*- C++ -*- ===//
29 /// SparseBitVector is an implementation of a bitvector that is sparse by only
331 const SparseBitVector<ElementSize> *BitVector;
349 if (BitVector->Elements.empty()) {
353 Iter = BitVector->Elements.begin();
381 if (Iter == BitVector->Elements.end()) {
433 SparseBitVectorIterator(): BitVector(NULL) {
438 bool end = false):BitVector(RHS) {
439 Iter = BitVector->Elements.begin();
  /external/llvm/lib/Target/ARM/
ARMMachineFunctionInfo.h 18 #include "llvm/ADT/BitVector.h"
82 BitVector GPRCS1Frames;
83 BitVector GPRCS2Frames;
84 BitVector DPRCSFrames;
  /external/llvm/unittests/ADT/
BitVectorTest.cpp 1 //===- llvm/unittest/ADT/BitVectorTest.cpp - BitVector tests --------------===//
13 #include "llvm/ADT/BitVector.h"
25 // Test both BitVector and SmallBitVector with the same suite of tests.
26 typedef ::testing::Types<BitVector, SmallBitVector> BitVectorTestTypes;
  /external/llvm/utils/TableGen/
CodeGenRegisters.h 20 #include "llvm/ADT/BitVector.h"
234 BitVector SubClasses;
259 BitVector TopoSigs;
316 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
324 // getSubClasses - Returns a constant BitVector of subclasses indexed by
327 const BitVector &getSubClasses() const { return SubClasses; }
350 const BitVector &getTopoSigs() const { return TopoSigs; }
645 // The returned BitVector will have a bit set for each register in Regs,
651 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
  /sdk/emulator/qtools/
q2g.cpp 10 #include "bitvector.h"

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