| /dalvik/vm/mterp/x86/ |
| OP_CONST_STRING_JUMBO.S | 28 SPILL(rIBASE)
|
| OP_DIV_LONG.S | 6 SPILL(rIBASE) # save rIBASE/%edx
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| OP_DIV_LONG_2ADDR.S | 7 SPILL(rIBASE) # save rIBASE/%edx
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| bindivLit16.S | 9 SPILL(rIBASE)
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| header.S | 38 sub FrameSize,%esp # Allocate storage for spill, locals & outs
50 will also have an associated spill location (mostly useful for those assigned
82 /* Spill offsets relative to %ebp */
103 /* for spill region: increase size by 48 (to keep 16-byte alignment) */
111 #define SPILL(reg) movl reg##,reg##_SPILL(%ebp)
|
| OP_CHECK_CAST.S | 41 SPILL(rIBASE)
71 SPILL(rIBASE)
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| entry.S | 34 * for 9 spill slots, 4 local slots, 5 arg slots to bring
39 /* Spill callee save regs */
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| OP_IGET.S | 14 SPILL(rIBASE) # preserve rIBASE
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| OP_IGET_WIDE.S | 12 SPILL(rIBASE) # preserve rIBASE
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| OP_IPUT.S | 15 SPILL (rIBASE)
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| OP_IPUT_WIDE.S | 12 SPILL(rIBASE)
|
| /external/llvm/test/CodeGen/X86/ |
| 2011-10-11-SpillDead.ll | 7 ; The call to @g forces a spill of that register.
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| reghinting.ll | 4 ;; The registers %x and %y must both spill across the finit call.
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| 2008-01-08-SchedulerCrash.ll | 3 ; Test scheduling a multi-use compare. We should neither spill flags
|
| /external/llvm/lib/CodeGen/ |
| SpillPlacement.cpp | 1 //===-- SpillPlacement.cpp - Optimal Spill Code Placement -----------------===//
10 // This file implements the spill code placement analysis.
24 // The energy function represents the expected spill code execution frequency,
44 INITIALIZE_PASS_BEGIN(SpillPlacement, "spill-code-placement",
45 "Spill Code Placement Analysis", true, true)
48 INITIALIZE_PASS_END(SpillPlacement, "spill-code-placement",
49 "Spill Code Placement Analysis", true, true)
101 /// mustSpill - Return True if this node is so biased that it must spill.
103 // Actually, we must spill if Bias < sum(weights).
297 // A node that must spill, or a node without any links is not going t
[all...] |
| CalcSpillWeights.cpp | 28 "Calculate spill weights", false, false)
32 "Calculate spill weights", false, false)
43 DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
127 // Don't recompute spill weight for an unspillable register.
180 // Weakly boost the spill weight of hinted registers.
|
| InlineSpiller.cpp | 50 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
51 cl::desc("Disable inline spill hoisting"));
67 // Variables that are valid during spill(), but used by multiple methods.
73 // All registers to spill to StackSlot, including the main register.
87 // True when all reaching defs were reloads: No spill is necessary.
96 // The preferred register to spill.
151 void spill(LiveRangeEdit &);
199 // When spilling a virtual register, we also spill any snippets it is connected
205 // spill slots which can be important in tight loops.
230 // %Reg = COPY %snip / SPILL %snip, fi
1268 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller
[all...] |
| /external/webkit/Source/JavaScriptCore/dfg/ |
| DFGJITCodeGenerator.h | 56 // These constants are used to set priorities for spill order for
60 SpillOrderConstant = 1, // no spill, and cheap fill
61 SpillOrderSpilled = 2, // no spill
62 SpillOrderJS = 4, // needs spill
63 SpillOrderCell = 4, // needs spill
64 SpillOrderInteger = 5, // needs spill and box
65 SpillOrderDouble = 6, // needs spill and convert
118 spill(spillMe);
126 spill(spillMe);
203 // Spill a VirtualRegister to the RegisterFile
204 void spill(VirtualRegister spillMe) function in class:JSC::DFG::JITCodeGenerator
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| stldst.ll | 36 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
38 ; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 1 //===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===//
56 return "Hexagon Expand Predicate Spill Code";
82 "Not a Frame Pointer, Nor a Spill Slot");
129 "Not a Frame Pointer, Nor a Spill Slot");
|
| /external/llvm/test/CodeGen/Hexagon/ |
| validate-offset.ll | 5 ; by 'Hexagon Expand Predicate Spill Code' pass.
|
| /external/llvm/test/CodeGen/PowerPC/ |
| buildvec_canonicalize.ll | 12 ; The fmul will spill a vspltisw to create a -0.0 vector used as the addend
|
| frame-size.ll | 10 ; Check that the RS spill slot has been allocated (because the estimate
|
| /external/llvm/test/CodeGen/Thumb/ |
| 2011-06-16-NoGPRs.ll | 6 ; to spill them.
|
| /external/llvm/test/CodeGen/Thumb2/ |
| inflate-regs.ll | 7 ; RAGreedy should split the range and use d16-d31 to avoid a spill.
|
