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  /external/llvm/test/Transforms/InstCombine/
2003-05-26-CastMiscompile.ll 5 %tmp.8 = zext i32 %tmp.3 to i64 ; <i64> [#uses=1]
2006-02-28-Crash.ll 5 %tmp203.upgrd.1 = zext i1 %tmp203 to i32 ; <i32> [#uses=1]
2007-03-19-BadTruncChangePR1261.ll 1 ; RUN: opt < %s -instcombine -S | grep zext
apint-cast-cast-to-and.ll 5 %Z = zext i41 %Y to i61
div-shift.ll 8 %conv = zext i16 %x to i32
20 %2 = zext i32 %1 to i64
30 ; CHECK-NEXT: %2 = zext i32 %1 to i64
34 %2 = zext i32 %1 to i64
zeroext-and-reduce.ll 5 %Y = zext i8 %X to i32 ; <i32> [#uses=1]
2012-05-28-select-hang.ll 10 %conv = zext i8 %0 to i32
14 %conv2 = zext i8 %conv1 to i32
20 %conv4 = zext i8 %1 to i32
21 %conv5 = zext i8 %conv3 to i32
31 %land.ext = zext i1 %2 to i32
compare-signs.ll 10 ; %3 = zext i1 %2 to i32 ; <i32> [#uses=1]
20 ; %3 = zext i1 %2 to i32 ;<i32> [#uses=1]
33 %3 = zext i1 %2 to i32 ; <i32> [#uses=1]
36 ; CHECK-NOT: zext
53 %5 = zext i1 %4 to i32 ; <i32> [#uses=1]
56 ; CHECK-NOT: zext
  /external/llvm/test/CodeGen/ARM/
fpcmp.ll 9 %tmp1 = zext i1 %tmp to i32 ; <i32> [#uses=1]
19 %tmp2 = zext i1 %tmp to i32 ; <i32> [#uses=1]
29 %tmp3 = zext i1 %tmp to i32 ; <i32> [#uses=1]
39 %tmp4 = zext i1 %tmp to i32 ; <i32> [#uses=1]
49 %tmp5 = zext i1 %tmp to i32 ; <i32> [#uses=1]
59 %tmp6 = zext i1 %tmp to i32 ; <i32> [#uses=1]
69 %tmp7 = zext i1 %tmp to i32 ; <i32> [#uses=1]
longMAC.ll 7 %conv = zext i32 %a to i64
8 %conv1 = zext i32 %b to i64
27 %conv = zext i32 %b to i64
28 %conv1 = zext i32 %a to i64
30 %conv2 = zext i32 %c to i64
  /external/llvm/test/CodeGen/X86/
shift-double.ll 5 %shift.upgrd.1 = zext i8 %C to i64 ; <i64> [#uses=1]
11 %shift.upgrd.2 = zext i8 %C to i64 ; <i64> [#uses=1]
17 %shift.upgrd.3 = zext i8 %C to i64 ; <i64> [#uses=1]
23 %shift.upgrd.4 = zext i8 %C to i32 ; <i32> [#uses=1]
26 %shift.upgrd.5 = zext i8 %Cv to i32 ; <i32> [#uses=1]
33 %shift.upgrd.6 = zext i8 %C to i16 ; <i16> [#uses=1]
36 %shift.upgrd.7 = zext i8 %Cv to i16 ; <i16> [#uses=1]
2008-09-11-CoalescerBug.ll 10 %2 = zext i16 %1 to i32 ; <i32> [#uses=1]
14 %6 = zext i1 %5 to i32 ; <i32> [#uses=1]
16 %8 = zext i1 %7 to i32 ; <i32> [#uses=1]
19 %11 = zext i1 %10 to i32 ; <i32> [#uses=1]
22 %14 = zext i1 %13 to i32 ; <i32> [#uses=1]
25 %17 = zext i1 %16 to i32 ; <i32> [#uses=1]
commute-two-addr.ll 45 %tmp21 = zext i32 %lb to i64
46 %tmp23 = zext i32 %ub to i64
49 %tmp28 = zext i8 %has_lb to i32
50 %tmp33 = zext i8 %has_ub to i32
52 %tmp38 = zext i8 %lb_inclusive to i32
54 %tmp43 = zext i8 %ub_inclusive to i32
pre-ra-sched.ll 21 %z1a = zext i8 %l1a to i32
24 %z1b = zext i8 %l1b to i32
31 %z2a = zext i8 %l2a to i32
34 %z2b = zext i8 %l2b to i32
40 %z3a = zext i8 %l3a to i32
43 %z3b = zext i8 %l3b to i32
zext-inreg-0.ll 18 %retval = zext i8 %tmp12 to i32
44 %retval = zext i8 %e to i32
49 %retval = zext i16 %e to i32
54 %retval = zext i8 %e to i64
59 %retval = zext i16 %e to i64
64 %retval = zext i32 %e to i64
  /external/llvm/test/CodeGen/XCore/
ladd_lsub_combine.ll 6 %0 = zext i32 %x to i64 ; <i64> [#uses=1]
7 %1 = zext i32 %y to i64 ; <i64> [#uses=1]
19 %0 = zext i32 %x to i64 ; <i64> [#uses=1]
20 %1 = zext i32 %y to i64 ; <i64> [#uses=1]
33 %0 = zext i32 %y to i64 ; <i64> [#uses=1]
46 %0 = zext i32 %x to i64 ; <i64> [#uses=1]
59 %0 = zext i32 %y to i64 ; <i64> [#uses=1]
misc-intrinsics.ll 7 declare i32 @llvm.xcore.zext(i32, i32)
33 define i32 @zext(i32 %a, i32 %b) {
34 ; CHECK: zext:
35 ; CHECK: zext r0, r1
36 %result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
42 ; CHECK: zext r0, 4
43 %result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
addsub64.ll 24 %0 = zext i32 %b to i64
25 %1 = zext i32 %c to i64
48 %0 = zext i32 %a to i64
49 %1 = zext i32 %b to i64
50 %2 = zext i32 %c to i64
51 %3 = zext i32 %d to i64
  /external/llvm/test/CodeGen/Thumb2/
longMACt.ll 7 %conv = zext i32 %a to i64
8 %conv1 = zext i32 %b to i64
27 %conv = zext i32 %b to i64
28 %conv1 = zext i32 %a to i64
30 %conv2 = zext i32 %c to i64
2009-08-10-ISelBug.ll 8 %2 = zext i8 %1 to i32 ; <i32> [#uses=1]
11 %5 = zext i8 %4 to i32 ; <i32> [#uses=1]
thumb2-sxt-uxt.ll 20 %r = zext i16 %z to i32
27 %r = zext i8 %z to i32
  /external/llvm/test/CodeGen/Hexagon/
cmpb_pred.ll 12 %selv = zext i1 %cmp to i32
22 %selv = zext i1 %cmp to i32
31 %selv = zext i1 %cmp to i32
41 %selv = zext i1 %cmp to i32
51 %selv = zext i1 %cmp to i32
60 %selv = zext i1 %cmp to i32
69 %selv = zext i1 %cmp to i32
78 %selv = zext i1 %cmp to i32
87 %selv = zext i1 %cmp to i32
combine_ir.ll 8 %1 = zext i32 %0 to i64
11 %3 = zext i32 %2 to i64
26 %1 = zext i16 %0 to i64
29 %3 = zext i16 %2 to i64
42 %1 = zext i8 %0 to i64
45 %3 = zext i8 %2 to i64
  /external/llvm/test/CodeGen/Mips/
madd-msub.ll 17 %conv = zext i32 %a to i64
18 %conv2 = zext i32 %b to i64
20 %conv4 = zext i32 %c to i64
49 %conv = zext i32 %c to i64
50 %conv2 = zext i32 %a to i64
51 %conv4 = zext i32 %b to i64
  /external/llvm/test/CodeGen/PowerPC/
rotl-64.ll 13 %Amt1 = zext i8 %Amt to i64
16 %Amt3 = zext i8 %Amt2 to i64

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