| /external/llvm/tools/llvm-objdump/ |
| MachODump.cpp | 259 STI(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
260 OwningPtr<const MCDisassembler> DisAsm(TheTarget->createMCDisassembler(*STI));
265 *MRI, *STI));
267 if (!InstrAnalysis || !AsmInfo || !STI || !DisAsm || !IP) {
|
| llvm-objdump.cpp | 282 OwningPtr<const MCSubtargetInfo> STI(
285 if (!STI) {
291 TheTarget->createMCDisassembler(*STI));
311 AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 41 const MCSubtargetInfo &STI;
45 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
47 : MCII(mcii), STI(sti), CTX(ctx) {
54 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
57 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) != 0;
60 Triple TT(STI.getTargetTriple());
342 const MCSubtargetInfo &STI,
344 return new ARMMCCodeEmitter(MCII, STI, Ctx);
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 62 MCSubtargetInfo &STI;
141 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0;
145 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0;
170 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
171 : MCTargetAsmParser(), STI(sti), Parser(parser) {
173 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
|
| ARMLoadStoreOptimizer.cpp | 67 const ARMSubtarget *STI;
[all...] |
| ARMConstantIslandPass.cpp | 260 const ARMSubtarget *STI;
386 STI = &MF->getTarget().getSubtarget<ARMSubtarget>();
470 if (isThumb2 && !STI->prefers32BitThumb())
[all...] |
| ARMExpandPseudoInsts.cpp | 44 const ARMSubtarget *STI;
623 if (!STI->hasV6T2Ops() &&
[all...] |
| ARMBaseInstrInfo.cpp | 89 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
91 Subtarget(STI) {
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.h | 27 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
|
| ARMInstPrinter.cpp | 63 const MCSubtargetInfo &STI) :
66 setAvailableFeatures(STI.getFeatureBits());
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 192 if (STI.hasV4TOps() && MBBI->getOpcode() == Hexagon::JMPR
|
| /external/clang/lib/Sema/ |
| SemaStmtAsm.cpp | 615 STI(TheTarget->createMCSubtargetInfo(TT, "", ""));
629 TargetParser(TheTarget->createMCAsmParser(*STI, *Parser));
634 TheTarget->createMCInstPrinter(1, *MAI, *MII, *MRI, *STI);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 37 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI)
39 RI(*this, STI), Subtarget(STI) {}
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 477 const MCSubtargetInfo &STI,
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 377 const MCSubtargetInfo &STI) {
|
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 711 const MCSubtargetInfo &STI) {
712 return new MBlazeDisassembler(STI);
|
| /external/llvm/tools/lto/ |
| LTOModule.cpp | 831 STI(T.createMCSubtargetInfo(_target->getTargetTriple(),
834 OwningPtr<MCTargetAsmParser> TAP(T.createMCAsmParser(*STI, *Parser.get()));
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 36 MCSubtargetInfo &STI;
89 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
92 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(X86::Mode64Bit));
105 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
106 : MCTargetAsmParser(), STI(sti), Parser(parser), InstInfo(0) {
109 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 44 MCSubtargetInfo &STI;
58 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
62 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 48 MCSubtargetInfo &STI;
125 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
131 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
134 return STI.getFeatureBits() & ARM::HasV6Ops;
137 return STI.getFeatureBits() & ARM::HasV7Ops;
140 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
144 return STI.getFeatureBits() & ARM::FeatureMClass;
245 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
252 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()))
[all...] |
