| /external/llvm/lib/Target/MSP430/ |
| MSP430TargetMachine.cpp | 28 StringRef TT,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS),
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| MSP430Subtarget.h | 33 MSP430Subtarget(const std::string &TT, const std::string &CPU,
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| /external/llvm/lib/Target/XCore/ |
| XCoreTargetMachine.cpp | 23 XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS),
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| XCoreSubtarget.h | 34 XCoreSubtarget(const std::string &TT, const std::string &CPU,
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| /external/clang/test/SemaTemplate/ |
| instantiate-template-template-parm.cpp | 34 template<template<int V> class TT> // expected-note{{parameter with type 'int'}}
37 template<typename T, template<T V> class TT>
39 X1<TT> x1; // expected-error{{has different template parameters}}
48 template <typename T, template <T, T> class TT, class R = TT<1, 2> >
64 template<template<int> class TT> struct X0
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| temp_arg.cpp | 4 template<typename> class TT>
|
| issue150.cpp | 44 template<typename T, typename U = T *, typename V = U const> class TT>
46 typedef TT<Z> type;
57 template<typename T, typename U = T *, typename V = U const> class TT>
59 typedef TT<Z> type;
63 template<typename T, typename U = T *, typename V = U const> class TT>
64 struct X<int, Z, TT> {
65 typedef TT<Z> type;
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| deduction.cpp | 60 template<template<typename> class TT, typename T1, typename Arg1, typename Arg2>
61 struct Replace<TT<T1>, Arg1, Arg2> {
62 typedef TT<typename Replace<T1, Arg1, Arg2>::type> type;
65 template<template<typename, typename> class TT, typename T1, typename T2,
67 struct Replace<TT<T1, T2>, Arg1, Arg2> {
68 typedef TT<typename Replace<T1, Arg1, Arg2>::type,
73 template<template<typename, typename> class TT, typename T1,
75 struct Replace<TT<T1, _2>, Arg1, Arg2> {
76 typedef TT<typename Replace<T1, Arg1, Arg2>::type, Arg2> type;
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| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| XCoreMCTargetDesc.cpp | 41 static MCRegisterInfo *createXCoreMCRegisterInfo(StringRef TT) {
47 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
50 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
54 static MCAsmInfo *createXCoreMCAsmInfo(const Target &T, StringRef TT) {
55 MCAsmInfo *MAI = new XCoreMCAsmInfo(T, TT);
65 static MCCodeGenInfo *createXCoreMCCodeGenInfo(StringRef TT, Reloc::Model RM,
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.h | 34 MCSubtargetInfo *createAArch64MCSubtargetInfo(StringRef TT, StringRef CPU,
46 MCAsmBackend *createAArch64AsmBackend(const Target &T, StringRef TT,
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| /external/llvm/lib/Target/CppBackend/ |
| CPPTargetMachine.h | 25 CPPTargetMachine(const Target &T, StringRef TT,
29 : TargetMachine(T, TT, CPU, FS, Options) {}
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCTargetDesc.cpp | 43 static MCRegisterInfo *createMBlazeMCRegisterInfo(StringRef TT) {
49 static MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
52 InitMBlazeMCSubtargetInfo(X, TT, CPU, FS);
56 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
57 Triple TheTriple(TT);
64 static MCCodeGenInfo *createMBlazeMCCodeGenInfo(StringRef TT, Reloc::Model RM,
76 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
82 Triple TheTriple(TT);
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCAsmInfo.cpp | 21 MipsMCAsmInfo::MipsMCAsmInfo(const Target &T, StringRef TT) {
22 Triple TheTriple(TT);
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| MipsMCTargetDesc.h | 45 MCAsmBackend *createMipsAsmBackendEB32(const Target &T, StringRef TT,
47 MCAsmBackend *createMipsAsmBackendEL32(const Target &T, StringRef TT,
49 MCAsmBackend *createMipsAsmBackendEB64(const Target &T, StringRef TT,
51 MCAsmBackend *createMipsAsmBackendEL64(const Target &T, StringRef TT,
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| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| NVPTXMCAsmInfo.cpp | 31 NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Target &T, const StringRef &TT) {
32 Triple TheTriple(TT);
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| NVPTXMCTargetDesc.cpp | 40 static MCRegisterInfo *createNVPTXMCRegisterInfo(StringRef TT) {
47 static MCSubtargetInfo *createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
50 InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
54 static MCCodeGenInfo *createNVPTXMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 43 static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
44 Triple TheTriple(TT);
54 static MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
57 InitPPCMCSubtargetInfo(X, TT, CPU, FS);
61 static MCAsmInfo *createPPCMCAsmInfo(const Target &T, StringRef TT) {
62 Triple TheTriple(TT);
79 static MCCodeGenInfo *createPPCMCCodeGenInfo(StringRef TT, Reloc::Model RM,
85 Triple T(TT);
92 Triple T(TT);
101 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
[all...] |
| /external/clang/test/CXX/temp/temp.arg/temp.arg.template/ |
| p3-0x.cpp | 5 template <template <class, class...> class TT, class T1, class... Rest>
6 struct eval<TT<T1, Rest...>> { };
20 template<template <int ...N> class TT> struct X0 { }; // expected-note{{previous non-type template parameter with type 'int' is here}}
30 template <T ...N> class TT> // expected-note{{previous non-type template parameter with type 'short' is here}}
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCAsmInfo.cpp | 18 HexagonMCAsmInfo::HexagonMCAsmInfo(const Target &T, StringRef TT) {
|
| /external/llvm/lib/Target/MSP430/MCTargetDesc/ |
| MSP430MCTargetDesc.cpp | 40 static MCRegisterInfo *createMSP430MCRegisterInfo(StringRef TT) {
46 static MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
49 InitMSP430MCSubtargetInfo(X, TT, CPU, FS);
53 static MCCodeGenInfo *createMSP430MCCodeGenInfo(StringRef TT, Reloc::Model RM,
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 40 static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
46 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
49 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
53 static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
|
| /external/skia/src/sfnt/ |
| SkOTTable_maxp.h | 28 struct TT : SkOTTableMaximumProfile_TT { } tt; member in union:SkOTTableMaximumProfile::Version
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetMachine.cpp | 39 MipsTargetMachine(const Target &T, StringRef TT,
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, isLittle, RM),
63 MipsebTargetMachine(const Target &T, StringRef TT,
67 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
72 MipselTargetMachine(const Target &T, StringRef TT,
76 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetMachine.cpp | 35 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
41 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42 Subtarget(TT, CPU, FS, is64Bit),
55 PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
60 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
65 PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
70 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| AMDGPUMCTargetDesc.cpp | 44 static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
50 static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
53 InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
57 static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
85 static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
|
