| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 101 unsigned Opc = N->getOpcode();
122 if (N.getOpcode() == ISD::FrameIndex) return false;
123 if (N.getOpcode() == ISD::TargetExternalSymbol ||
124 N.getOpcode() == ISD::TargetGlobalAddress)
128 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
132 if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
133 N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
153 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR)
[all...] |
| MBlazeInstrInfo.cpp | 45 if (MI->getOpcode() == MBlaze::LWI) {
64 if (MI->getOpcode() == MBlaze::SWI) {
137 unsigned LastOpc = LastInst->getOpcode();
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
162 if (MBlaze::isCondBranchOpcode(SecondLastInst->getOpcode()) &&
163 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
165 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
173 if (MBlaze::isUncondBranchOpcode(SecondLastInst->getOpcode()) &&
174 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
223 if (!MBlaze::isUncondBranchOpcode(I->getOpcode()) &
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 99 switch (MI.getOpcode()) {
144 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
194 if (LastInst->getOpcode() == NVPTX::GOTO) {
197 } else if (LastInst->getOpcode() == NVPTX::CBranch) {
216 if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
217 LastInst->getOpcode() == NVPTX::GOTO) {
226 if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
227 LastInst->getOpcode() == NVPTX::GOTO) {
243 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| FPMover.cpp | 90 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
91 MI->getOpcode() == SP::FpNEGD) {
95 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) {
106 if (MI->getOpcode() == SP::FpMOVD)
108 else if (MI->getOpcode() == SP::FpNEGD)
110 else if (MI->getOpcode() == SP::FpABSD)
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 145 inline unsigned getOpcode() const;
364 /// getOpcode - Return the SelectionDAG opcode value for this node. For
368 unsigned getOpcode() const { return (unsigned short)NodeType; }
782 inline unsigned SDValue::getOpcode() const {
783 return Node->getOpcode();
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 95 switch (I->getOpcode()) {
104 return TTI->getCFInstrCost(I->getOpcode());
124 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType());
129 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy);
134 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy);
139 return TTI->getMemoryOpCost(I->getOpcode(), ValTy,
145 return TTI->getMemoryOpCost(I->getOpcode(), I->getType(),
162 return TTI->getCastInstrCost(I->getOpcode(), I->getType(), SrcTy);
170 return TTI->getVectorInstrCost(I->getOpcode(),
179 return TTI->getVectorInstrCost(I->getOpcode(),
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 86 switch(MI->getOpcode()) {
94 if (MI->getOpcode() == Hexagon::TFR_condset_rr ||
95 MI->getOpcode() == Hexagon::TFR_condset_rr_f) {
99 else if (MI->getOpcode() == Hexagon::TFR_condset_rr64_f) {
130 if (MI->getOpcode() == Hexagon::TFR_condset_ri ) {
135 } else if (MI->getOpcode() == Hexagon::TFR_condset_ri_f ) {
151 if (MI->getOpcode() == Hexagon::TFR_condset_ir ) {
156 } else if (MI->getOpcode() == Hexagon::TFR_condset_ir_f ) {
179 if (MI->getOpcode() == Hexagon::TFR_condset_ii ) {
188 } else if (MI->getOpcode() == Hexagon::TFR_condset_ii_f )
[all...] |
| HexagonCFGOptimizer.cpp | 70 switch(MI->getOpcode()) {
107 int Opc = MI->getOpcode();
159 if ((MI->getOpcode() == Hexagon::JMP_c) ||
160 (MI->getOpcode() == Hexagon::JMP_cNot)) {
172 IsUnconditionalJump(LayoutSucc->front().getOpcode())) {
179 IsUnconditionalJump(JumpAroundTarget->back().getOpcode()) &&
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 106 switch (I->getOpcode()) {
201 switch (I->getOpcode()) {
314 bool isLeftShift = I.getOpcode() == Instruction::Shl;
319 if (I.getOpcode() != Instruction::AShr &&
337 if (I.getOpcode() != Instruction::AShr)
346 if (BO->getOpcode() == Instruction::Mul && isLeftShift)
372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
386 if (I.getOpcode() == Instruction::Shl)
389 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift");
408 switch (Op0BO->getOpcode()) {
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 58 int Opcode = MI->getOpcode();
80 int Opcode = MI->getOpcode();
209 if (IsBRU(LastInst->getOpcode())) {
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
235 unsigned SecondLastOpc = SecondLastInst->getOpcode();
241 && IsBRU(LastInst->getOpcode())) {
253 if (IsBRU(SecondLastInst->getOpcode()) &&
254 IsBRU(LastInst->getOpcode())) {
263 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) {
[all...] |
| XCoreISelDAGToDAG.cpp | 99 if (Addr.getOpcode() == ISD::ADD) {
115 if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) {
120 if (Addr.getOpcode() == ISD::ADD) {
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
136 if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) {
141 if (Addr.getOpcode() == ISD::ADD) {
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
157 switch (N->getOpcode()) {
237 if (Chain->getOpcode() != ISD::TokenFactor)
260 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCBranchSelector.cpp | 115 if (I->getOpcode() != PPC::BCC || I->getOperand(2).isImm()) {
152 if (I->getOpcode() == PPC::BCC) {
163 } else if (I->getOpcode() == PPC::BDNZ) {
165 } else if (I->getOpcode() == PPC::BDNZ8) {
167 } else if (I->getOpcode() == PPC::BDZ) {
169 } else if (I->getOpcode() == PPC::BDZ8) {
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) &&
60 (TII.canCauseFpMLxStall(MI->getOpcode()) ||
|
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
|
| TargetInsn.java | 61 return new TargetInsn(getOpcode(), getPosition(), registers, target);
75 Dop opcode = getOpcode().getOppositeTest();
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
|
| /dalvik/dx/src/com/android/dx/io/instructions/ |
| OneRegisterDecodedInstruction.java | 52 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| RegisterRangeDecodedInstruction.java | 57 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| TwoRegisterDecodedInstruction.java | 61 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| /dalvik/dx/src/com/android/dx/merge/ |
| InstructionTransformer.java | 70 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
80 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
90 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
100 boolean isJumbo = (one.getOpcode() == Opcodes.CONST_STRING_JUMBO);
|
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| SimpleInsn.java | 51 return new SimpleInsn(getOpcode(), getPosition(), registers);
|
| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| OneRegisterDecodedInstruction.java | 52 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| RegisterRangeDecodedInstruction.java | 57 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| TwoRegisterDecodedInstruction.java | 61 getFormat(), getOpcode(), newIndex, getIndexType(),
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| FillArrayDataInsn.java | 103 return new FillArrayDataInsn(getOpcode(), getPosition(),
113 return new FillArrayDataInsn(getOpcode(), getPosition(),
|
