| /dalvik/dx/src/com/android/dx/io/instructions/ |
| FiveRegisterDecodedInstruction.java | 88 getFormat(), getOpcode(), newIndex, getIndexType(),
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| FourRegisterDecodedInstruction.java | 79 getFormat(), getOpcode(), newIndex, getIndexType(),
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| ThreeRegisterDecodedInstruction.java | 70 getFormat(), getOpcode(), newIndex, getIndexType(),
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| InstructionCodec.java | 110 out.write(codeUnit(insn.getOpcode(), insn.getA()));
127 out.write(codeUnit(insn.getOpcode(), relativeTarget));
163 codeUnit(insn.getOpcode(), insn.getLiteralByte()),
182 codeUnit(insn.getOpcode(), insn.getA()),
202 out.write(codeUnit(insn.getOpcode(), insn.getA()), relativeTarget);
220 codeUnit(insn.getOpcode(), insn.getA()),
247 int opcode = insn.getOpcode();
270 codeUnit(insn.getOpcode(), insn.getA()),
291 codeUnit(insn.getOpcode(), insn.getA()),
312 codeUnit(insn.getOpcode(), insn.getA())
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| FixedAddressChecker.cpp | 40 if (B->getOpcode() != BO_Assign)
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| /external/dexmaker/src/dx/java/com/android/dx/io/instructions/ |
| FiveRegisterDecodedInstruction.java | 88 getFormat(), getOpcode(), newIndex, getIndexType(),
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| FourRegisterDecodedInstruction.java | 79 getFormat(), getOpcode(), newIndex, getIndexType(),
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| ThreeRegisterDecodedInstruction.java | 70 getFormat(), getOpcode(), newIndex, getIndexType(),
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 119 if (Inst.getOpcode() == AArch64::Bcc
126 if (Inst.getOpcode() == AArch64::Bcc
134 unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
136 if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType
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| /external/webkit/Source/JavaScriptCore/interpreter/ |
| Interpreter.h | 76 Opcode getOpcode(OpcodeID id)
152 bool isCallBytecode(Opcode opcode) { return opcode == getOpcode(op_call) || opcode == getOpcode(op_construct) || opcode == getOpcode(op_call_eval); }
|
| /frameworks/compile/libbcc/lib/AndroidBitcode/ |
| ABCExpandVAArgPass.cpp | 39 if (inst->getOpcode() == llvm::Instruction::VAArg) {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 42 if (MI->getOpcode() == SP::LDri ||
43 MI->getOpcode() == SP::LDFri ||
44 MI->getOpcode() == SP::LDDFri) {
61 if (MI->getOpcode() == SP::STri ||
62 MI->getOpcode() == SP::STFri ||
63 MI->getOpcode() == SP::STDFri) {
151 if (I->getOpcode() == SP::BA) {
177 unsigned Opcode = I->getOpcode();
268 if (I->getOpcode() != SP::BA
269 && I->getOpcode() != SP::BCON
[all...] |
| DelaySlotFiller.cpp | 139 if (slot->getOpcode() == SP::RET)
142 if (slot->getOpcode() == SP::RETL) {
144 if (I->getOpcode() != SP::RESTORErr)
237 switch(MI->getOpcode()) {
296 if (candidate->getOpcode() == SP::UNIMP)
308 switch (I->getOpcode()) {
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| /dalvik/dx/src/com/android/dx/rop/code/ |
| DexTranslationAdvice.java | 67 opcode.getOpcode() == RegOps.SUB) {
77 switch (opcode.getOpcode()) {
|
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| DexTranslationAdvice.java | 67 opcode.getOpcode() == RegOps.SUB) {
77 switch (opcode.getOpcode()) {
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 97 Rop opcode = originalRopInsn.getOpcode();
114 RegOps.flippedIfOpcode(opcode.getOpcode()), null);
117 opcode.getOpcode(), null);
148 Rop opcode = originalRopInsn.getOpcode();
152 opcode.getOpcode() != RegOps.CONST) {
160 if (opcode.getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
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| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 97 Rop opcode = originalRopInsn.getOpcode();
114 RegOps.flippedIfOpcode(opcode.getOpcode()), null);
117 opcode.getOpcode(), null);
148 Rop opcode = originalRopInsn.getOpcode();
152 opcode.getOpcode() != RegOps.CONST) {
160 if (opcode.getOpcode() == RegOps.MOVE_RESULT_PSEUDO) {
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.cpp | 89 switch (iter->getOpcode()) {
108 if (tmp->getOpcode() == AMDGPU::ENDLOOP
109 || tmp->getOpcode() == AMDGPU::ENDIF
110 || tmp->getOpcode() == AMDGPU::ELSE) {
240 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_STORE;
244 return get(MI.getOpcode()).TSFlags & AMDGPU_FLAG_REGISTER_LOAD;
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| R600InstrInfo.cpp | 40 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
44 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
179 if (!isALUInstr(MI->getOpcode()))
183 int SrcIdx = getOperandIdx(MI->getOpcode(), OpTable[j][0]);
188 getOperandIdx(MI->getOpcode(), OpTable[j][1])).getImm();
218 if (isPredicateSetter(MI->getOpcode()))
248 if (!isJump(static_cast<MachineInstr *>(I)->getOpcode())) {
256 unsigned LastOpc = LastInst->getOpcode();
258 !isJump(static_cast<MachineInstr *>(--I)->getOpcode())) {
264 while (!isPredicateSetter(predSet->getOpcode())) {
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| IntegerDivision.cpp | 335 assert((Rem->getOpcode() == Instruction::SRem ||
336 Rem->getOpcode() == Instruction::URem) &&
342 if (Rem->getOpcode() == Instruction::SRem) {
352 if (!BO || BO->getOpcode() != Instruction::URem)
368 assert(UDiv->getOpcode() == Instruction::UDiv && "Non-udiv in expansion?");
385 assert((Div->getOpcode() == Instruction::SDiv ||
386 Div->getOpcode() == Instruction::UDiv) &&
395 if (Div->getOpcode() == Instruction::SDiv) {
405 if (!BO || BO->getOpcode() != Instruction::UDiv)
430 assert((Rem->getOpcode() == Instruction::SRem |
[all...] |
| /external/llvm/include/llvm/IR/ |
| InstrTypes.h | 116 return I->getOpcode() == Instruction::Alloca ||
117 I->getOpcode() == Instruction::Load ||
118 I->getOpcode() == Instruction::VAArg ||
119 I->getOpcode() == Instruction::ExtractValue ||
120 (I->getOpcode() >= CastOpsBegin && I->getOpcode() < CastOpsEnd);
326 BinaryOps getOpcode() const {
327 return static_cast<BinaryOps>(Instruction::getOpcode());
597 Instruction::CastOps getOpcode() const {
598 return Instruction::CastOps(Instruction::getOpcode());
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 342 if (Const32->getOpcode() == HexagonISD::CONST32 &&
715 if ((Const32->getOpcode() == HexagonISD::CONST32) &&
718 if (Base.getOpcode() == ISD::TargetGlobalAddress) {
792 if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
799 } else if (MulOp0.getOpcode() == ISD::LOAD) {
818 if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
825 } else if (MulOp1.getOpcode() == ISD::LOAD) {
857 if (N0.getOpcode() == ISD::SETCC) {
859 if (N00.getOpcode() == ISD::SIGN_EXTEND_INREG) {
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 194 if (MI->getOpcode() == PPC::CMPWI) {
198 } else if (MI->getOpcode() == PPC::CMPDI) {
202 } else if (MI->getOpcode() == PPC::CMPLWI) {
206 } else if (MI->getOpcode() == PPC::CMPLDI) {
320 if (LastI->getOpcode() != PPC::BCC)
397 if (DefInstr && (DefInstr->getOpcode() == PPC::ORI8 ||
398 DefInstr->getOpcode() == PPC::ORI)) {
402 if (DefInstr2 && (DefInstr2->getOpcode() == PPC::LIS8 ||
403 DefInstr2->getOpcode() == PPC::LIS)) {
424 } else if (DefInstr && (DefInstr->getOpcode() == PPC::LI8 |
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 87 unsigned Opcode = MI.getOpcode();
127 unsigned Opcode = MI.getOpcode();
230 assert((MI.getOpcode() == PPC::MTCRF ||
231 MI.getOpcode() == PPC::MFOCRF ||
232 MI.getOpcode() == PPC::MTCRF8) &&
244 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
|
| /external/llvm/lib/Analysis/ |
| PHITransAddr.cpp | 34 if (Inst->getOpcode() == Instruction::Add &&
200 return AddAsInput(ConstantExpr::getCast(Cast->getOpcode(),
208 if (CastI->getOpcode() == Cast->getOpcode() &&
262 if (Inst->getOpcode() == Instruction::Add &&
274 if (BOp->getOpcode() == Instruction::Add)
303 if (BO->getOpcode() == Instruction::Add &&
391 CastInst *New = CastInst::Create(Cast->getOpcode(),
425 if (Inst->getOpcode() == Instruction::Add &&
|
