| /external/llvm/unittests/IR/ |
| MDBuilderTest.cpp | 38 Value *Op = MD1->getOperand(0);
52 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(0)));
53 EXPECT_TRUE(isa<ConstantInt>(R1->getOperand(1)));
54 ConstantInt *C0 = cast<ConstantInt>(R1->getOperand(0));
55 ConstantInt *C1 = cast<ConstantInt>(R1->getOperand(1));
66 EXPECT_EQ(R0->getOperand(0), R0);
67 EXPECT_EQ(R1->getOperand(0), R1);
68 EXPECT_TRUE(R0->getNumOperands() == 1 || R0->getOperand(1) == 0);
69 EXPECT_TRUE(R1->getNumOperands() == 1 || R1->getOperand(1) == 0);
77 EXPECT_TRUE(isa<MDString>(R0->getOperand(0)))
[all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 38 DestName = getRegName(MI->getOperand(0).getReg());
39 Src1Name = getRegName(MI->getOperand(1).getReg());
40 Src2Name = getRegName(MI->getOperand(2).getReg());
41 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
46 Src2Name = getRegName(MI->getOperand(2).getReg());
47 Src1Name = getRegName(MI->getOperand(1).getReg());
48 DestName = getRegName(MI->getOperand(0).getReg());
54 Src2Name = getRegName(MI->getOperand(2).getReg());
55 Src1Name = getRegName(MI->getOperand(1).getReg());
56 DestName = getRegName(MI->getOperand(0).getReg())
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 81 switch (MI->getOperand(0).getImm()) {
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
155 MI->getOperand(0).getReg() == ARM::SP &&
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 112 MI->getOperand(0).getReg(),
113 MI->getOperand(1).getReg());
121 MI->getOperand(0).getReg(),
122 MI->getOperand(1).getReg());
130 MI->getOperand(0).getReg(),
131 MI->getOperand(1).getReg());
137 unsigned maskedRegister = MI->getOperand(0).getReg();
145 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(),
146 MI->getOperand(1).getFPImm()->getValueAPF()
150 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg()
[all...] |
| SILowerControlFlow.cpp | 179 unsigned Reg = MI.getOperand(0).getReg();
180 unsigned Vcc = MI.getOperand(1).getReg();
189 Skip(MI, MI.getOperand(2));
197 unsigned Dst = MI.getOperand(0).getReg();
198 unsigned Src = MI.getOperand(1).getReg();
207 Skip(MI, MI.getOperand(2));
216 unsigned Dst = MI.getOperand(0).getReg();
217 unsigned Src = MI.getOperand(1).getReg();
230 unsigned Dst = MI.getOperand(0).getReg();
231 unsigned Vcc = MI.getOperand(1).getReg()
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 34 unsigned char SH = MI->getOperand(2).getImm();
35 unsigned char MB = MI->getOperand(3).getImm();
36 unsigned char ME = MI->getOperand(4).getImm();
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
67 unsigned char SH = MI->getOperand(2).getImm();
68 unsigned char ME = MI->getOperand(3).getImm();
89 unsigned Code = MI->getOperand(OpNo).getImm();
91 unsigned CCReg = MI->getOperand(OpNo+1).getReg();
139 int Value = MI->getOperand(OpNo).getImm()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 101 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
102 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
116 Base = Addr.getOperand(0);
122 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
123 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
126 Base = Addr.getOperand(0).getOperand(0);
137 Base = Addr.getOperand(0);
143 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
144 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 40 isa<ConstantInt>(I->getOperand(2)))
46 (CheapToScalarize(BO->getOperand(0), isConstant) ||
47 CheapToScalarize(BO->getOperand(1), isConstant)))
51 (CheapToScalarize(CI->getOperand(0), isConstant) ||
52 CheapToScalarize(CI->getOperand(1), isConstant)))
73 if (!isa<ConstantInt>(III->getOperand(2)))
75 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue();
80 return III->getOperand(1);
84 return FindScalarElement(III->getOperand(0), EltNo);
88 unsigned LHSWidth = SVI->getOperand(0)->getType()->getVectorNumElements()
[all...] |
| InstCombineShifts.cpp | 23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType());
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
92 if (MaskedValueIsZero(I->getOperand(0),
95 return CanEvaluateTruncated(I->getOperand(0), Ty);
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) &&
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC);
117 CI = dyn_cast<ConstantInt>(I->getOperand(1));
132 if (MaskedValueIsZero(I->getOperand(0)
[all...] |
| InstCombineAndOrXor.cpp | 135 Value *X = Op->getOperand(0);
259 Value *ShVal = Op->getOperand(0);
349 !isa<ConstantInt>(LHSI->getOperand(1))) return 0;
351 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1));
386 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold");
387 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
502 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
504 X = I->getOperand(0);
514 if (ConstantInt *C = dyn_cast<ConstantInt>(I->getOperand(1)))
516 X = I->getOperand(0)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitTFRCondSets.cpp | 90 int DestReg = MI->getOperand(0).getReg();
91 int SrcReg1 = MI->getOperand(2).getReg();
92 int SrcReg2 = MI->getOperand(3).getReg();
108 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
112 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
120 int DestReg = MI->getOperand(0).getReg();
121 int SrcReg1 = MI->getOperand(2).getReg();
128 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
133 addReg(MI->getOperand(1).getReg()).
134 addImm(MI->getOperand(3).getImm())
[all...] |
| HexagonAsmPrinter.h | 71 int value = MI->getOperand(OpNo).getImm();
77 int value = MI->getOperand(OpNo).getImm();
83 const MachineOperand &MO1 = MI->getOperand(OpNo);
84 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
93 const MachineOperand &MO1 = MI->getOperand(OpNo);
94 const MachineOperand &MO2 = MI->getOperand(OpNo+1);
105 if (MI->getOperand(OpNo).isImm()) {
106 O << "$+" << MI->getOperand(OpNo).getImm()*4;
108 printOp(MI->getOperand(OpNo), O);
122 if (MI->getOperand(OpNo).isImm())
[all...] |
| HexagonRegisterInfo.cpp | 128 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
148 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister(), false,
150 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(FrameSize+Offset);
171 getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
172 MI.getOperand(0).getReg();
187 MI.getOperand(FIOperandNum).ChangeToRegister(dstReg, false, false,true);
188 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
215 MI.getOperand(FIOperandNum).ChangeToRegister(resReg, false, false,true);
216 MI.getOperand(FIOperandNum+1).ChangeToImmediate(0);
221 MI.getOperand(FIOperandNum).ChangeToRegister(getStackRegister()
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsDirectObjLower.cpp | 26 assert(Inst.getOperand(2).isImm());
28 int64_t Shift = Inst.getOperand(2).getImm();
34 Inst.getOperand(2).setImm(Shift);
63 assert(InstIn.getOperand(2).isImm());
64 int64_t pos = InstIn.getOperand(2).getImm();
65 assert(InstIn.getOperand(3).isImm());
66 int64_t size = InstIn.getOperand(3).getImm();
72 InstIn.getOperand(2).setImm(pos - 32);
78 InstIn.getOperand(3).setImm(size - 32);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 426 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
430 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
444 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
448 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
454 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
464 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
482 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
486 GetNegatedExpression(Op.getOperand(0), DAG,
488 Op.getOperand(1));
491 GetNegatedExpression(Op.getOperand(1), DAG
[all...] |
| LegalizeFloatTypes.cpp | 110 return BitConvertToInteger(N->getOperand(0));
124 BitConvertToInteger(N->getOperand(0)),
125 BitConvertToInteger(N->getOperand(1)));
135 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
138 NewOp, N->getOperand(1));
149 SDValue Op = GetSoftenedFloat(N->getOperand(0));
155 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
156 GetSoftenedFloat(N->getOperand(1)) };
168 SDValue Op = GetSoftenedFloat(N->getOperand(0));
179 SDValue LHS = GetSoftenedFloat(N->getOperand(0))
[all...] |
| LegalizeIntegerTypes.cpp | 155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
157 Op.getValueType(), Op, N->getOperand(1));
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
164 Op.getValueType(), Op, N->getOperand(1));
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
207 SDValue InOp = N->getOperand(0);
238 GetSplitVector(N->getOperand(0), Lo, Hi);
264 SDValue Op = GetPromotedInteger(N->getOperand(0))
[all...] |
| /external/llvm/lib/Target/Hexagon/InstPrinter/ |
| HexagonInstPrinter.cpp | 91 const MCOperand& MO = MI->getOperand(OpNo);
106 const MCOperand& MO = MI->getOperand(OpNo);
111 O << MI->getOperand(OpNo).getImm();
127 O << MI->getOperand(OpNo).getImm();
132 O << -MI->getOperand(OpNo).getImm();
142 const MCOperand& MO0 = MI->getOperand(OpNo);
143 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
151 const MCOperand& MO0 = MI->getOperand(OpNo);
152 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
159 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression")
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 310 isInt32Immediate(N->getOperand(1).getNode(), Imm);
356 SDValue N0 = N->getOperand(0);
357 SDValue N1 = N->getOperand(1);
384 SDValue Srl = N1.getOperand(0);
406 Srl.getOperand(0),
487 BaseReg = N.getOperand(0);
489 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
511 BaseReg = N.getOperand(0);
513 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
516 ShReg = N.getOperand(1)
[all...] |
| ARMExpandPseudoInsts.cpp | 78 const MachineOperand &MO = OldMI.getOperand(i);
387 bool DstIsDead = MI.getOperand(OpIdx).isDead();
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++));
423 MachineOperand MO = MI.getOperand(SrcOpIdx)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
92 Base = Addr.getOperand(0);
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
99 Base = Addr.getOperand(1);
100 Offset = Addr.getOperand(0).getOperand(0);
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
104 Base = Addr.getOperand(0);
105 Offset = Addr.getOperand(1).getOperand(0)
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 71 MachineOperand &MO = MI->getOperand(i);
80 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
81 MI->getOperand(1).isImm() &&
82 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
83 MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
85 unsigned DstReg = MI->getOperand(0).getReg();
86 unsigned InsReg = MI->getOperand(2).getReg();
87 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?")
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 88 SrcReg = MI.getOperand(1).getReg();
89 DstReg = MI.getOperand(0).getReg();
103 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104 MI->getOperand(2).isFI()) {
105 FrameIndex = MI->getOperand(2).getIndex();
106 return MI->getOperand(0).getReg();
121 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122 MI->getOperand(2).isFI())
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 55 const MCOperand &MOImm = MI->getOperand(OpNum);
65 unsigned ExtImm = MI->getOperand(OpNum).getImm();
94 const MCOperand &Imm12Op = MI->getOperand(OpNum);
118 const MCOperand &MO = MI->getOperand(OpNum);
125 const MCOperand &ImmROp = MI->getOperand(OpNum);
133 const MCOperand &ImmSOp = MI->getOperand(OpNum);
142 const MCOperand &ImmSOp = MI->getOperand(OpNum);
143 const MCOperand &ImmROp = MI->getOperand(OpNum - 1);
156 const MCOperand &CRx = MI->getOperand(OpNum);
165 const MCOperand &ScaleOp = MI->getOperand(OpNum)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 145 SDValue N0 = N.getOperand(0);
211 if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
212 !MatchAddress(N.getNode()->getOperand(1), AM))
215 if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
216 !MatchAddress(N.getNode()->getOperand(0), AM))
225 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
229 if (!MatchAddress(N.getOperand(0), AM) &&
233 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
421 Node->getOperand(0), Node->getOperand(1)
[all...] |
