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  /sdk/eclipse/plugins/com.android.ide.eclipse.ndk/src/com/android/ide/eclipse/ndk/internal/templates/
TemplatedInputStream.java 30 private char[] mSub;
49 if (mSub != null) {
50 char c = mSub[mPos++];
51 if (mPos >= mSub.length)
52 mSub = null;
67 mSub = str.toCharArray();
  /external/llvm/test/CodeGen/Mips/
fmadd1.ll 17 ; CHECK: msub.s
40 ; 32R2NAN: msub.s
41 ; 64R2NAN: msub.s
59 ; CHECK: msub.d
82 ; 32R2NAN: msub.d
83 ; 64R2NAN: msub.d
madd-msub.ll 35 ; CHECK: msub
57 ; CHECK: msub
dsp-r1.ll 323 ; CHECK: msub $ac{{[0-9]}}
325 %1 = tail call i64 @llvm.mips.msub(i64 %a0, i32 %a1, i32 %a2)
329 declare i64 @llvm.mips.msub(i64, i32, i32) nounwind readnone
    [all...]
  /external/webkit/Source/WebCore/mathml/
mathtags.in 19 msub interfaceName=MathMLInlineContainerElement
  /ndk/tests/build/mips-fp4/
build.sh 21 find_instruction "msub.d" mips-fp4-test1-2.s
  /external/llvm/test/CodeGen/PowerPC/
fma.ll 2 ; RUN: egrep "fn?madd|fn?msub" | count 8
  /external/webkit/Source/WebCore/css/
mathml.css 48 msub, msup {
53 msub > * + * {
  /external/aac/libFDK/include/mips/
cplx_mul.h 113 "msub %[a_Im], %[b_Im];\n"
142 "msub %[a_Im], %[b_Im];\n"
  /external/llvm/test/CodeGen/AArch64/
dp-3source.ll 23 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
31 ; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
  /external/llvm/test/MC/Mips/
mips-alu-instructions.s 75 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
96 msub $6,$7
mips64-alu-instructions.s 75 # CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
94 msub $6,$7
  /external/llvm/lib/Target/Mips/
MipsInstrFPU.td 372 def MSUB_S : MADDS_FT<"msub.s", FGR32, IIFmulSingle, fsub>, MADDS_FM<5, 0>;
382 def MSUB_D32 : MADDS_FT<"msub.d", AFGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
394 def MSUB_D64 : MADDS_FT<"msub.d", FGR64, IIFmulDouble, fsub>, MADDS_FM<5, 1>;
MipsInstrInfo.td 85 // MAdd*/MSub* nodes
90 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
    [all...]
MipsISelLowering.h 74 MSub,
  /external/valgrind/main/none/tests/mips32/
MIPS32int.c 563 printf("MSUB\n");
564 TESTINST3a("msub $t0, $t1", 0x6, 0x2, t0, t1);
565 TESTINST3a("msub $t0, $t1", 0x55, 0x28, t0, t1);
566 TESTINST3a("msub $t0, $t1", 0x18, 0xfff, t0, t1);
567 TESTINST3a("msub $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
568 TESTINST3a("msub $t0, $t1", 0xffffffff, 0x1, t0, t1);
569 TESTINST3a("msub $t0, $t1", 0x1, 0xffffffff, t0, t1);
570 TESTINST3a("msub $t0, $t1", 0x2, 0x6, t0, t1);
571 TESTINST3a("msub $t0, $t1", 0x356, 0x555, t0, t1);
    [all...]
MIPS32int.stdout.exp 406 MSUB
407 msub $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0xffffffff LO 0xfffffff4
408 msub $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0xffffffff LO 0xfffff2b8
409 msub $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0xffffffff LO 0xfffe8018
410 msub $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
411 msub $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0x00000001
412 msub $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0x00000001
413 msub $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0xffffffff LO 0xfffffff4
414 msub $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0xffffffff LO 0xffee3672
    [all...]
MIPS32int.stdout.exp-BE 406 MSUB
407 msub $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0xffffffff LO 0xfffffff4
408 msub $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0xffffffff LO 0xfffff2b8
409 msub $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0xffffffff LO 0xfffe8018
410 msub $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
411 msub $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0x00000001
412 msub $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0x00000001
413 msub $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0xffffffff LO 0xfffffff4
414 msub $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0xffffffff LO 0xffee3672
    [all...]
MIPS32int.stdout.exp-mips32 386 MSUB
387 msub $t0, $t1 :: rs 0x00000006 rt 0x00000002 HI 0xffffffff LO 0xfffffff4
388 msub $t0, $t1 :: rs 0x00000055 rt 0x00000028 HI 0xffffffff LO 0xfffff2b8
389 msub $t0, $t1 :: rs 0x00000018 rt 0x00000fff HI 0xffffffff LO 0xfffe8018
390 msub $t0, $t1 :: rs 0x7fffffff rt 0x7fffffff HI 0xc0000000 LO 0xffffffff
391 msub $t0, $t1 :: rs 0xffffffff rt 0x00000001 HI 0x00000000 LO 0x00000001
392 msub $t0, $t1 :: rs 0x00000001 rt 0xffffffff HI 0x00000000 LO 0x00000001
393 msub $t0, $t1 :: rs 0x00000002 rt 0x00000006 HI 0xffffffff LO 0xfffffff4
394 msub $t0, $t1 :: rs 0x00000356 rt 0x00000555 HI 0xffffffff LO 0xffee3672
    [all...]
  /external/valgrind/main/VEX/priv/
guest_mips_toIR.c     [all...]
  /external/llvm/test/MC/Disassembler/Mips/
mips32.txt 264 # CHECK: msub $6, $7
mips32_le.txt 264 # CHECK: msub $6, $7
mips32r2.txt 273 # CHECK: msub $6, $7
mips32r2_le.txt 273 # CHECK: msub $6, $7
  /external/llvm/test/MC/AArch64/
basic-a64-instructions.s     [all...]

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