Lines Matching refs:x1
31 #define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1
36 #define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1
41 #define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1
46 #define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1
51 #define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1
56 #define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1
61 #define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1
64 #define TIMPANI_MREF_RESERVED_M 0x1
75 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1
87 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1
100 #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1
114 #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1
121 #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1
137 #define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1
142 #define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
147 #define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1
152 #define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1
157 #define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1
162 #define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1
167 #define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1
170 #define TIMPANI_TXADC3_EN_RESERVED_M 0x1
181 #define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1
186 #define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
191 #define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1
196 #define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1
201 #define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1
206 #define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1
211 #define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1
214 #define TIMPANI_TXADC4_EN_RESERVED_M 0x1
244 #define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1
249 #define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1
256 #define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1
261 #define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1
266 #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1
271 #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1
274 #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1
276 #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1
287 #define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1
292 #define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1
300 x1
305 #define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1
310 #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1
315 #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1
317 #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1
320 #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1
331 #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
336 #define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1
341 #define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1
346 #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1
351 #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
356 #define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1
361 #define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1
364 #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1
366 #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1
377 #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1
390 #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1
406 #define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1
411 #define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
416 #define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1
421 #define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1
426 #define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1
431 #define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1
436 #define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1
439 #define TIMPANI_TXADC1_EN_RESERVED_M 0x1
450 #define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1
455 #define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
460 #define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1
465 #define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1
470 #define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1
475 #define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1
480 #define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1
482 #define TIMPANI_TXADC2_EN_RESERVED_M 0x1
494 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1
501 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1
509 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1
516 #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1
530 #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1
537 #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1
545 #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1
552 #define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1
555 #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1
557 #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1
569 #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1
576 #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1
584 #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1
591 #define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1
594 #define TIMPANI_TXADC_CTL3_RESERVED_M 0x1
605 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1
610 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1
622 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1
627 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1
641 #define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1
646 #define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1
656 #define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1
659 #define TIMPANI_TXFE3_RESERVED_2_M 0x1
670 #define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1
675 #define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1
685 #define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1
687 #define TIMPANI_TXFE4_RESERVED_2_M 0x1
699 #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
704 #define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1
709 #define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1
714 #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1
719 #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
724 #define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1
729 #define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1
731 #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1
734 #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1
747 #define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1
752 #define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1
757 #define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1
760 #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1
762 #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1
774 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1
779 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1
784 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1
805 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1
809 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1
811 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1
822 #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1
835 #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1
842 #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1
847 #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1
850 #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1
861 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1
874 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1
886 #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1
900 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1
905 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1
912 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1
930 #define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1
935 #define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1
941 #define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1
947 #define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1
962 #define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1
967 #define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1
972 #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1
980 #define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1
982 #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1
984 #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1
996 #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1
1009 #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1
1021 #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1
1034 #define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1
1039 #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1
1046 #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1
1054 #define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
1059 #define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1
1061 #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1
1064 #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
1075 #define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1
1080 #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1
1087 #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1
1095 #define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
1100 #define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1
1102 #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1
1105 #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
1116 #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1
1129 #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1
1141 #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1
1155 x1
1162 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1
1170 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1
1177 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1
1191 #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1
1214 #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1
1242 #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
1255 #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
1266 #define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1
1270 #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1
1271 #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1
1282 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1
1287 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1
1292 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1
1297 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1
1302 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1
1307 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1
1312 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1
1316 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1
1317 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1
1329 #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1
1334 #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1
1339 #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1
1344 #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1
1349 #define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1
1354 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1
1359 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1
1362 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1
1364 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1
1375 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1
1380 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1
1386 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1
1391 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1
1396 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1
1401 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1
1406 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1
1409 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1
1411 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1
1422 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1
1489 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1
1555 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1
1611 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1
1615 #define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1
1626 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1
1682 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1
1686 #define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1
1697 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1
1720 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1
1749 #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1
1754 #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1
1759 #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1
1765 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1
1771 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1
1776 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1
1779 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1
1781 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1
1792 #define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1
1797 #define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1
1802 #define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1
1807 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1
1812 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1
1817 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1
1822 #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1
1836 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1
1841 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1
1846 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1
1851 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1
1856 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1
1861 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1
1866 #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1
1880 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1
1885 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1
1890 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1
1895 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1
1900 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1
1905 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1
1909 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1
1912 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1
1914 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1
1926 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1
1931 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1
1936 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1
1941 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1
1946 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1
1951 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1
1965 #define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1
1970 #define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1
1975 #define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1
1979 #define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1
1994 #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1
2004 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1
2009 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1
2030 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1
2035 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1
2040 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1
2047 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1
2050 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1
2052 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1
2066 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1
2071 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1
2076 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1
2084 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1
2086 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1
2089 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1
2100 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1
2107 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1
2115 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1
2122 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1
2135 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
2140 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
2146 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
2152 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1
2157 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1
2164 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
2177 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
2185 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
2195 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1
2200 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1
2202 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1
2205 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
2216 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1
2221 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1
2226 #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
2232 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
2261 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1
2284 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1
2311 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
2316 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
2322 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
2329 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1
2334 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1
2340 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
2354 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
2361 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
2371 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1
2376 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1
2379 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1
2381 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
2392 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1
2397 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1
2402 #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
2409 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
2437 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1
2460 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1
2487 #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1
2500 #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1
2520 #define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1
2525 #define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1
2530 #define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1
2535 #define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1
2541 #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1
2549 #define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1
2551 #define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1
2562 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1
2570 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1
2577 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1
2600 #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1
2606 #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1
2612 #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1
2617 #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1
2619 #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1
2631 #define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1
2636 #define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1
2641 #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1
2654 #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1
2671 #define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1
2677 #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1
2685 #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
2692 #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
2697 #define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1
2709 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1
2714 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
2721 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1
2726 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
2731 #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1
2742 #define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1
2750 #define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1
2766 #define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1
2782 #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1
2790 #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1
2806 #define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1
2811 #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1
2822 #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1
2842 #define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1
2847 #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1
2859 #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1
2876 #define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1
2881 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1
2886 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1
2891 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1
2896 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1
2910 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1
2915 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1
2920 #define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1
2925 #define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1
2930 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1
2937 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1
2950 #define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1
2962 #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1
2967 #define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1
2980 #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1
2992 #define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1
2997 #define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1
3002 #define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1
3007 #define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1
3012 #define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1
3017 #define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1
3022 #define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1
3025 #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1
3027 #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1
3039 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1
3061 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1
3090 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1
3095 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1
3100 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1
3115 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1
3120 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1
3122 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1
3125 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1
3149 #define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1
3165 #define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1
3170 #define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1
3174 #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1
3175 #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1
3192 #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1
3197 #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1
3201 #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1
3202 #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1
3230 #define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1
3309 #define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1
3344 #define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1
3377 #define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1
3407 #define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1
3421 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1
3427 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1
3431 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1
3442 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1
3451 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1
3460 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1
3475 #define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1
3484 #define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1
3496 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1
3505 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1
3514 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1
3529 #define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1
3537 #define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1
3542 #define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1
3552 #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1
3559 #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1
3574 #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1
3580 #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1
3594 #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1
3601 #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1
3609 #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1
3616 #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1
3630 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1
3637 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1
3645 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1
3652 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1
3660 #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1
3662 #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1
3672 #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1
3676 #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1
3677 #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1
3690 #define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1
3706 #define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1
3722 #define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1
3739 #define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1
3744 #define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1
3747 #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1
3749 #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1
3756 #define TIMPANI_CDC_ARB_CLK_EN_M 0x1
3759 #define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1
3772 #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1
3781 #define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1
3829 #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
3836 #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
3844 #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
3851 #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
3864 #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1
3892 #define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1
3914 #define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1
3935 #define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1
3951 #define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1
3980 #define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1
4007 #define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1
4029 #define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1
4061 #define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1
4064 #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1
4065 #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1
4076 #define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1
4081 #define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1
4086 #define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1
4091 #define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1
4096 #define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1
4100 #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1
4101 #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1
4126 #define TIMPANI_CDC_ANC1_RX_NS_POR 0x1
4136 #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1
4160 #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1
4162 #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1
4181 #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
4185 #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1
4186 #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1
4250 #define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1
4255 #define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1
4260 #define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1
4265 #define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1
4270 #define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1
4274 #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1
4275 #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1
4300 #define TIMPANI_CDC_ANC2_RX_NS_POR 0x1
4310 #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1
4334 #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1
4336 #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1
4355 #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
4359 #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1
4360 #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1
4449 #define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1
4452 #define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1
4465 #define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1
4469 #define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1
4495 #define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1
4589 #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1
4595 #define TIMPANI_CDC_COMP_HALT_M 0x1
4597 #define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1
