Lines Matching full:"0 x2"
44 #define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2
64 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2
75 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2
86 #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2
102 #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
109 #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2
155 #define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2
202 #define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2
251 #define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2
270 #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2
297 #define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2
316 #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2
365 #define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2
387 #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2
398 #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2
444 #define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2
491 #define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2
511 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2
518 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2
525 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2
532 #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2
548 #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2
555 #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2
562 #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2
566 #define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2
588 #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2
595 #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2
602 #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2
606 #define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2
631 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2
669 #define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2
676 #define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2
701 #define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2
708 #define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2
755 #define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2
787 #define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2
819 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2
835 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2
857 #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2
868 #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2
875 #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2
896 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2
907 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2
918 #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2
939 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2
1013 #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2
1017 #define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2
1039 #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2
1050 #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2
1061 #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2
1081 #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
1088 #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2
1097 #define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2
1124 #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2
1131 #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2
1140 #define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2
1162 #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2
1173 #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2
1184 #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2
1200 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2
1207 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2
1214 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2
1221 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2
1237 #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2
1256 #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2
1284 #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
1295 #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2
1303 #define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2
1352 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2
1401 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2
1450 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2
1472 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2
1531 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2
1590 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2
1634 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2
1654 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2
1698 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2
1718 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2
1737 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2
1790 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2
1842 #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2
1888 #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2
1931 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2
2027 #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2
2042 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2
2075 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2
2079 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2
2114 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2
2118 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2
2140 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2
2147 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2
2154 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2
2161 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2
2187 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
2204 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
2220 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
2227 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
2239 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2
2270 #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
2276 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
2303 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2
2322 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2
2360 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2
2377 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2
2393 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2
2400 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2
2412 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2
2444 #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2
2450 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2
2478 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2
2497 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2
2524 #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2
2539 #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2
2578 #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2
2582 0x2
2593 #define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2
2602 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2
2609 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2
2616 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2
2622 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2
2641 #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2
2653 #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2
2684 #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2
2695 #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2
2720 #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2
2727 #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
2734 #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2
2773 #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2
2839 #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2
2846 #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2
2870 #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2
2880 #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2
2907 #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2
2917 #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2
2993 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2
3000 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2
3024 #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2
3040 #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2
3084 #define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2
3106 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2
3125 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2
3180 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2
3214 #define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2
3241 #define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2
3272 #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2
3309 #define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2
3414 #define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2
3459 #define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2
3492 #define TIMPANI_CDC_BYPASS_CTL1_POR 0x2
3504 #define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2
3543 #define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2
3561 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2
3567 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2
3585 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2
3593 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2
3601 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2
3643 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2
3651 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2
3659 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2
3703 #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2
3709 #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2
3717 #define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2
3726 #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2
3732 #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2
3748 #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2
3755 #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2
3762 #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2
3769 #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2
3785 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2
3792 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2
3799 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2
3806 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2
3832 #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2
3851 #define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2
3872 #define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2
3893 #define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2
3920 #define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2
3954 #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2
3962 #define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2
4027 #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
4034 #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
4041 #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2
4048 #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2
4065 #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2
4096 #define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2
4123 #define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2
4150 #define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2
4159 #define TIMPANI_CDC_BYPASS_CTL4_POR 0x2
4171 #define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2
4210 #define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2
4246 #define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2
4273 #define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2
4358 #define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2
4407 #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2
4470 #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2
4581 #define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2
4630 #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2
4693 #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2
4817 #define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2
4837 #define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2
4872 #define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2
4998 #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2
