Lines Matching refs:x1
16 #define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1
21 #define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1
26 #define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1
31 #define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1
36 #define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1
41 #define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1
46 #define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1
49 #define TIMPANI_MREF_RESERVED_M 0x1
63 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1
74 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1
85 #define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1
101 #define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1
108 #define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1
127 #define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1
132 #define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
137 #define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1
142 #define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1
147 #define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1
152 #define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1
157 #define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1
160 #define TIMPANI_TXADC3_EN_RESERVED_M 0x1
174 #define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1
179 #define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
184 #define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1
189 #define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1
194 #define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1
199 #define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1
204 #define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1
207 #define TIMPANI_TXADC4_EN_RESERVED_M 0x1
245 #define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1
250 #define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1
257 #define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1
262 #define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1
267 #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1
272 #define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1
275 #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1
277 #define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1
291 #define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1
296 #define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1
303 #define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1
308 #define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1
313 #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1
318 #define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1
321 #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1
323 #define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1
337 #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
342 #define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1
347 #define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1
352 #define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1
357 #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
362 #define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1
367 #define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1
370 #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1
372 #define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1
386 #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1
397 #define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1
416 #define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1
421 #define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
426 #define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1
431 #define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1
436 #define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1
441 #define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1
446 #define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1
449 #define TIMPANI_TXADC1_EN_RESERVED_M 0x1
463 #define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1
468 #define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1
473 #define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1
478 #define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1
483 #define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1
488 #define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1
493 #define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1
496 #define TIMPANI_TXADC2_EN_RESERVED_M 0x1
510 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1
517 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1
524 #define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1
531 #define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1
547 #define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1
554 #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1
561 #define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1
568 #define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1
571 #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1
573 #define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1
587 #define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1
594 #define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1
601 #define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1
608 #define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1
611 #define TIMPANI_TXADC_CTL3_RESERVED_M 0x1
625 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1
630 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1
641 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1
646 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1
663 #define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1
668 #define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1
678 #define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1
681 #define TIMPANI_TXFE3_RESERVED_2_M 0x1
695 #define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1
700 #define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1
710 #define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1
713 #define TIMPANI_TXFE4_RESERVED_2_M 0x1
727 #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
732 #define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1
737 #define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1
742 #define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1
747 #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1
752 #define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1
757 #define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1
760 #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1
762 #define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1
779 #define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1
784 #define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1
789 #define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1
792 #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1
794 #define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1
808 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1
813 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1
818 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1
836 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1
840 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1
842 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1
856 #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1
867 #define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1
874 #define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1
879 #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1
881 #define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1
895 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1
906 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1
917 #define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1
933 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1
938 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1
945 #define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1
966 #define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1
971 #define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1
978 #define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1
984 #define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1
1002 #define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1
1007 #define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1
1012 #define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1
1019 #define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1
1022 #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1
1023 #define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1
1038 #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1
1049 #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1
1060 #define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1
1075 #define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1
1080 #define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1
1087 #define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1
1094 #define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
1099 #define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1
1102 #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1
1104 #define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
1118 #define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1
1123 #define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1
1130 #define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1
1137 #define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1
1142 #define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1
1145 #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1
1147 #define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1
1161 #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1
1172 #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1
1183 #define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1
1199 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1
1206 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1
1213 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1
1220 #define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1
1236 #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1
1255 #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1
1283 #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
1294 #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1
1304 #define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1
1308 #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1
1309 #define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1
1323 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1
1328 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1
1333 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1
1338 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1
1343 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1
1348 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1
1353 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1
1357 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1
1358 #define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1
1372 #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1
1377 #define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1
1382 #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1
1387 #define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1
1392 #define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1
1397 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1
1402 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1
1406 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1
1407 #define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1
1421 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1
1426 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1
1432 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1
1437 #define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1
1442 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1
1447 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1
1452 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1
1455 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1
1457 #define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1
1471 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1
1530 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1
1589 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1
1635 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1
1639 #define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1
1653 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1
1699 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1
1703 #define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1
1717 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1
1736 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1
1764 #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1
1769 #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1
1774 #define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1
1781 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1
1787 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1
1792 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1
1795 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1
1797 #define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1
1811 #define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1
1816 #define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1
1821 #define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1
1826 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1
1831 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1
1836 #define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1
1841 #define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1
1857 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1
1862 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1
1867 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1
1872 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1
1877 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1
1882 #define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1
1887 #define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1
1903 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1
1908 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1
1913 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1
1918 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1
1923 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1
1928 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1
1932 #define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1
1936 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1
1937 #define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1
1952 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1
1957 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1
1962 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1
1967 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1
1972 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1
1977 #define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1
1994 #define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1
1999 #define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1
2004 #define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1
2008 #define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1
2026 #define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1
2036 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1
2041 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1
2064 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1
2069 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1
2074 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1
2081 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1
2084 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1
2086 #define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1
2103 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1
2108 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1
2113 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1
2120 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1
2123 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1
2125 #define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1
2139 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1
2146 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1
2153 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1
2160 #define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1
2175 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
2180 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
2186 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
2192 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1
2197 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1
2203 #define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
2219 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
2226 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
2236 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1
2241 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1
2244 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1
2246 #define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
2259 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1
2264 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1
2269 #define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
2275 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
2302 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1
2321 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1
2348 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1
2353 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1
2359 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1
2365 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1
2370 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1
2376 #define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1
2392 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1
2399 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1
2409 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1
2414 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1
2417 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1
2419 #define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1
2433 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1
2438 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1
2443 #define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1
2449 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1
2477 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1
2496 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1
2523 #define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1
2534 #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1
2556 #define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1
2561 #define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1
2566 #define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1
2571 #define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1
2577 #define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1
2584 #define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1
2587 #define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1
2601 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1
2608 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1
2615 #define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1
2640 #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1
2646 #define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1
2652 #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1
2657 #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1
2658 #define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1
2673 #define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1
2678 #define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1
2683 #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1
2694 #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1
2713 #define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1
2719 #define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1
2726 #define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
2733 #define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1
2738 #define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1
2752 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1
2757 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
2765 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1
2770 #define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1
2776 #define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1
2790 #define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1
2798 #define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1
2818 #define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1
2838 #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1
2845 #define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1
2864 #define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1
2869 #define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1
2879 #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1
2901 #define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1
2906 #define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1
2916 #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1
2935 #define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1
2940 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1
2945 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1
2950 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1
2955 #define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1
2972 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1
2977 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1
2982 #define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1
2987 #define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1
2992 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1
2999 #define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1
3014 #define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1
3025 #define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1
3030 #define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1
3041 #define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1
3056 #define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1
3061 #define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1
3066 #define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1
3071 #define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1
3076 #define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1
3081 #define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1
3086 #define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1
3089 #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1
3091 #define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1
3105 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1
3124 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1
3152 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1
3157 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1
3162 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1
3177 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1
3182 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1
3185 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1
3187 #define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1
3217 #define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1
3237 #define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1
3242 #define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1
3246 #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1
3247 #define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1
3268 #define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1
3273 #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1
3277 #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1
3278 #define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1
3312 #define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1
3417 #define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1
3462 #define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1
3507 #define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1
3546 #define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1
3562 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1
3568 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1
3572 #define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1
3586 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1
3594 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1
3602 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1
3620 #define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1
3629 #define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1
3644 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1
3652 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1
3660 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1
3678 #define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1
3687 #define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1
3694 #define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1
3704 #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1
3710 #define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1
3727 #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1
3733 #define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1
3749 #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1
3756 #define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1
3763 #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1
3770 #define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1
3786 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1
3793 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1
3800 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1
3807 #define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1
3816 #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1
3820 #define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1
3833 #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1
3837 #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1
3838 #define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1
3854 #define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1
3875 #define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1
3896 #define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1
3916 #define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1
3921 #define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1
3925 #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1
3926 #define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1
3935 #define TIMPANI_CDC_ARB_CLK_EN_M 0x1
3939 #define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1
3955 #define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1
3965 #define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1
4028 #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
4035 #define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
4042 #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1
4049 #define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1
4064 #define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1
4099 #define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1
4126 #define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1
4153 #define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1
4174 #define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1
4213 #define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1
4249 #define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1
4276 #define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1
4320 #define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1
4324 #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1
4325 #define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1
4339 #define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1
4344 #define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1
4349 #define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1
4354 #define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1
4359 #define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1
4363 #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1
4364 #define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1
4398 #define TIMPANI_CDC_ANC1_RX_NS_POR 0x1
4410 #define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1
4442 #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1
4446 #define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1
4471 #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
4475 #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1
4476 #define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1
4562 #define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1
4567 #define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1
4572 #define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1
4577 #define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1
4582 #define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1
4586 #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1
4587 #define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1
4621 #define TIMPANI_CDC_ANC2_RX_NS_POR 0x1
4633 #define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1
4665 #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1
4669 #define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1
4694 #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1
4698 #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1
4699 #define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1
4818 #define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1
4822 #define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1
4838 #define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1
4842 #define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1
4875 #define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1
5001 #define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1
5009 #define TIMPANI_CDC_COMP_HALT_M 0x1
5013 #define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1
