Lines Matching refs:ISD
62 namespace ISD {
74 /// ISD::SCALAR_TO_VECTOR node or a BUILD_VECTOR node where only the low
79 /// and all operands of the specified node are ISD::UNDEF.
81 } // end llvm:ISD namespace
366 /// are the opcode values in the ISD and <target>ISD namespaces. For
371 /// \<target\>ISD namespace).
372 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
375 /// memory-referencing opcode (in the \<target\>ISD namespace and
378 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
622 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
892 : SDNode(ISD::HANDLENODE, DebugLoc(), getSDVTList(MVT::Other)) {
983 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
990 return N->getOpcode() == ISD::LOAD ||
991 N->getOpcode() == ISD::STORE ||
992 N->getOpcode() == ISD::PREFETCH ||
993 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
994 N->getOpcode() == ISD::ATOMIC_SWAP ||
995 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
996 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
997 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
998 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
999 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1000 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1001 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1002 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1003 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1004 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1005 N->getOpcode() == ISD::ATOMIC_LOAD ||
1006 N->getOpcode() == ISD::ATOMIC_STORE ||
1067 return Op == ISD::ATOMIC_CMP_SWAP;
1072 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1073 N->getOpcode() == ISD::ATOMIC_SWAP ||
1074 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1075 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1076 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1077 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1078 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1079 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1080 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1081 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1082 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1083 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1084 N->getOpcode() == ISD::ATOMIC_LOAD ||
1085 N->getOpcode() == ISD::ATOMIC_STORE;
1105 return N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1106 N->getOpcode() == ISD::INTRINSIC_VOID ||
1107 N->getOpcode() == ISD::PREFETCH ||
1130 : SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {
1157 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1165 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
1180 return N->getOpcode() == ISD::Constant ||
1181 N->getOpcode() == ISD::TargetConstant;
1189 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
1223 return N->getOpcode() == ISD::ConstantFP ||
1224 N->getOpcode() == ISD::TargetConstantFP;
1244 return N->getOpcode() == ISD::GlobalAddress ||
1245 N->getOpcode() == ISD::TargetGlobalAddress ||
1246 N->getOpcode() == ISD::GlobalTLSAddress ||
1247 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1255 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1263 return N->getOpcode() == ISD::FrameIndex ||
1264 N->getOpcode() == ISD::TargetFrameIndex;
1273 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1282 return N->getOpcode() == ISD::JumpTable ||
1283 N->getOpcode() == ISD::TargetJumpTable;
1298 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
1306 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
1342 return N->getOpcode() == ISD::ConstantPool ||
1343 N->getOpcode() == ISD::TargetConstantPool;
1356 : SDNode(ISD::TargetIndex, DebugLoc(), getSDVTList(VT)),
1365 return N->getOpcode() == ISD::TargetIndex;
1376 : SDNode(ISD::BasicBlock, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb) {
1383 return N->getOpcode() == ISD::BasicBlock;
1407 return N->getOpcode() == ISD::BUILD_VECTOR;
1420 : SDNode(ISD::SRCVALUE, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
1427 return N->getOpcode() == ISD::SRCVALUE;
1435 : SDNode(ISD::MDNODE_SDNODE, DebugLoc(), getSDVTList(MVT::Other)), MD(md) {}
1441 return N->getOpcode() == ISD::MDNODE_SDNODE;
1450 : SDNode(ISD::Register, DebugLoc(), getSDVTList(VT)), Reg(reg) {
1457 return N->getOpcode() == ISD::Register;
1466 : SDNode(ISD::RegisterMask, DebugLoc(), getSDVTList(MVT::Untyped)),
1473 return N->getOpcode() == ISD::RegisterMask;
1493 return N->getOpcode() == ISD::BlockAddress ||
1494 N->getOpcode() == ISD::TargetBlockAddress;
1503 : SDNode(ISD::EH_LABEL, dl, getSDVTList(MVT::Other)), Label(L) {
1510 return N->getOpcode() == ISD::EH_LABEL;
1520 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
1529 return N->getOpcode() == ISD::ExternalSymbol ||
1530 N->getOpcode() == ISD::TargetExternalSymbol;
1535 ISD::CondCode Condition;
1537 explicit CondCodeSDNode(ISD::CondCode Cond)
1538 : SDNode(ISD::CONDCODE, DebugLoc(), getSDVTList(MVT::Other)),
1543 ISD::CondCode get() const { return Condition; }
1546 return N->getOpcode() == ISD::CONDCODE;
1553 ISD::CvtCode CvtCode;
1556 unsigned NumOps, ISD::CvtCode Code)
1557 : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
1562 ISD::CvtCode getCvtCode() const { return CvtCode; }
1565 return N->getOpcode() == ISD::CONVERT_RNDSAT;
1575 : SDNode(ISD::VALUETYPE, DebugLoc(), getSDVTList(MVT::Other)),
1583 return N->getOpcode() == ISD::VALUETYPE;
1598 LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands,
1599 unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
1605 assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
1610 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
1615 ISD::MemIndexedMode getAddressingMode() const {
1616 return ISD::MemIndexedMode((SubclassData >> 2) & 7);
1620 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
1623 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
1626 return N->getOpcode() == ISD::LOAD ||
1627 N->getOpcode() == ISD::STORE;
1631 /// LoadSDNode - This class is used to represent ISD::LOAD nodes.
1636 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1638 : LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3,
1649 ISD::LoadExtType getExtensionType() const {
1650 return ISD::LoadExtType(SubclassData & 3);
1657 return N->getOpcode() == ISD::LOAD;
1661 /// StoreSDNode - This class is used to represent ISD::STORE nodes.
1666 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
1668 : LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4,
1687 return N->getOpcode() == ISD::STORE;
1797 namespace ISD {
1802 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
1803 Ld->getAddressingMode() == ISD::UNINDEXED;
1810 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
1817 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
1824 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
1831 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
1838 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
1846 St->getAddressingMode() == ISD::UNINDEXED;
1865 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
