Lines Matching refs:ISD
159 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
160 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
198 int ISD = TLI->InstructionOpcodeToISD(Opcode);
199 assert(ISD && "Invalid opcode");
203 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
213 if (!TLI->isOperationExpand(ISD, LT.second)) {
239 int ISD = TLI->InstructionOpcodeToISD(Opcode);
240 assert(ISD && "Invalid opcode");
263 if (TLI->isOperationLegalOrPromote(ISD, DstLT.second))
274 if (!TLI->isOperationExpand(ISD, DstLT.second))
298 if (!TLI->isOperationExpand(ISD, DstLT.second))
332 int ISD = TLI->InstructionOpcodeToISD(Opcode);
333 assert(ISD && "Invalid opcode");
336 if (ISD == ISD::SELECT) {
339 ISD = ISD::VSELECT;
344 if (!TLI->isOperationExpand(ISD, LT.second)) {
384 unsigned ISD = 0;
405 case Intrinsic::sqrt: ISD = ISD::FSQRT; break;
406 case Intrinsic::sin: ISD = ISD::FSIN; break;
407 case Intrinsic::cos: ISD = ISD::FCOS; break;
408 case Intrinsic::exp: ISD = ISD::FEXP; break;
409 case Intrinsic::exp2: ISD = ISD::FEXP2; break;
410 case Intrinsic::log: ISD = ISD::FLOG; break;
411 case Intrinsic::log10: ISD = ISD::FLOG10; break;
412 case Intrinsic::log2: ISD = ISD::FLOG2; break;
413 case Intrinsic::fabs: ISD = ISD::FABS; break;
414 case Intrinsic::floor: ISD = ISD::FFLOOR; break;
415 case Intrinsic::ceil: ISD = ISD::FCEIL; break;
416 case Intrinsic::trunc: ISD = ISD::FTRUNC; break;
417 case Intrinsic::rint: ISD = ISD::FRINT; break;
418 case Intrinsic::pow: ISD = ISD::FPOW; break;
419 case Intrinsic::fma: ISD = ISD::FMA; break;
420 case Intrinsic::fmuladd: ISD = ISD::FMA; break; // FIXME: mul + add?
425 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
435 if (!TLI->isOperationExpand(ISD, LT.second)) {
